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| 144 rgb segment & 177 common driver for 65,536 colo r stn lcd august. 12. 200 2 ver. 1.1 S6B33B0A contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or me chanical, for any purpose, without the express written permission of lcd driver ic team. precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semicondu ctor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area , the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate ( board or glass) or product design stage. 2. always test and inspect products un der the environment with no penetration of light.
144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 2 S6B33B0A specification revision history version content date 0 . 0 original neglect the more past version than version 0.0 mar. 2002 0.1 add the schottky barrier diode connection between vee and vss at the system application diagram may. 2002 0.2 append the schottky barrier diode specification append the addressing condition for the 256 color and 4.096 color mode june. 2002 0.3 append the power on/off sequences . june. 2002 1.0 definition of tbd items july. 2002 1.1 modify reg_out range: 1.8 to 1.9v - > 1.8 to 2.2v add the dc spec for vin2 , dc2in, vin45 . aug. 2002 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ ............ 1 features ................................ ................................ ................................ ................................ .................... 1 block diagram ................................ ................................ ................................ ................................ ......... 2 pad configuration ................................ ................................ ................................ ................................ . 3 pin configuration ................................ ................................ ................................ ................................ ... 5 pad center coordinat es ................................ ................................ ................................ ...................... 6 pin description ................................ ................................ ................................ ................................ ....... 11 pin description ................................ ................................ ................................ ................................ ....... 12 functional descripti on ................................ ................................ ................................ ....................... 15 mpu interface ................................ ................................ ................................ ................................ .. 15 display data ram ................................ ................................ ................................ ............................. 19 instruction descript ion ................................ ................................ ................................ ...................... 28 instruction paramete r ................................ ................................ ................................ ........................ 56 power on/off seqence ................................ ................................ ................................ ......................... 59 specifications ................................ ................................ ................................ ................................ ......... 61 absolute maximum rat ings ................................ ................................ ................................ ........... 61 operating voltage ................................ ................................ ................................ ......................... 61 dc characteristics ( 1) ................................ ................................ ................................ ................... 62 dc characteristics ( 2) ................................ ................................ ................................ ................... 63 dc characteristics ( 3) ................................ ................................ ................................ ................... 64 dc characteristics ( 4) ................................ ................................ ................................ ................... 65 dc characteristics ( 5) ................................ ................................ ................................ ................... 66 ac c haracteristics ................................ ................................ ................................ ......................... 67 system application d iagram ................................ ................................ ................................ ............... 71 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 1 introduction S6B33B0A is a mid - display - size - compatible driver for liquid crystal dot matrix gray - scale graphic systems. with on - chip cr oscillator c ircuit, the display - timing signal is generated without being sent from mpu. a lso, it is capable of using 8bit/16bit data bus alternatively and operating with 68 / 80 - series mpu in asynchronous. due to the lcd driving signal ( 144 rgb x 177 output) correspondi ng to the display data and the internal bit - map display ram of 144 176 16 - bit, S6B33B0A is capable of operating max. 1 44 rgb x 177 dot lcd panels in low - power consumption. being the segment rgb 3 - output, one pixel is 16 - bit data and S6B33B0A can max disp lay 65,536 color. features driver output - 144 rgb x 177 g ray s cale f unction - 65,536 color display of r : 32 gray scale, g : 64 gray scale, b : 32 gray scale - 4,096 color display of r : 16 gray scale, g : 16 gray scale, b : 16 gray scale - 256 color display of r : 8 g ray scale, g : 8 gray scale, b : 4 gray scale on - chip display data ram - capacity: 144 x 16 x 176 = 405.504k bits - burst ram write function display mode - normal display mode: entire duty displaying - partial display mode: partial duty displaying - standby mode: int ernal display clocks off - area scroll mode: particular area scrolling microprocessor interface - 8 - bit /16 bit parallel bi - directional interface with 6800 - series or 8080 - series - 3/4 pin spi (only write operation) on - chip low power analog circuit - on - chip cr o scillator (internal cap. & external resistor), external clock available - voltage converter / voltage regulator / voltage follower - on - chip electronic contrast control ( 256 steps) operating voltage range - v dd : 1.8 to 3.3 [ v ] (without internal regulator), 2.4 to 3.3 [v] (with internal regulator) - vin1: 2.4 to 3.6 [v] - display operating voltage (v1) : 2.0 to 4.0 v - lcd operating voltage range : max. 20 v low power consumption - 650 m a typ. (refer to dc characteristics (2)) package type - cog (output pad pitch min. 40 m m) 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 2 block diagram com driving circuit lcd system control circuit bus holder mpu interface cs2 cs1b db<15:0> display data ram 176 x 2304 mpu system control circuit instruction decoder seg driving circuit y - address control circuit i/o buffer x - address control circuit status oscillator circuit voltage converter/ voltage regulator/ voltage follower ps rstb vrn vmin vrp v1in reg_enb reg_out power regulator circuit decoder circuit 2304 432 176 pm fr cl vss vee vcc vin2 vin45 vout45 c11p c11m c12m c12p vin1 v1t c21p c22m c22p c21m c23p c23m c24p c24m c31p c31m intrs vdd3, vdd3r vdd,vddo v0in vmout v1out osc5 osc2 osc3 osc4 osc1 sega0 segb0 - - - segc0 com0 - - - com176 sega143 segb143 segc143 dc2out dc2in mpu[1:0] wrb d/i(rs) rdb cdir vss,vssa,vssb,vsso figure 1 . block diagram S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 3 pad configuration ....................... .. ............ . x y (0,0) s6b33b0 pad 777 1 219 279 220 278 836 778 tom align key figure 2 . S6B33B0A chip pad configuration table 1 . s6b33b0 a pad dimensions size item pad no. x y unit chip size (with s/l 120 m m ) 20644 2870 1 to 219 90 pad pitch 220 to 278, 279 to 777, 778 to 836 40 1 to 219 70 70 220 to 278, , 778 to 836 150 25 bumped pad size 279 to 777 25 150 bumped pad height all pad 17 m m 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 4 cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m 30 m m 30 m m 30 m m 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m ( - 8100,780) (8618, - 855) ( - 8270, - 928) (8670,820) figure 3 . cog align key coordinate figure 4 . ilb align key coordinat e tom(teg on main chip) coordinate cof align key coordinate 220um ( - 8270 , - 40) ( - 8050 , 540 ) 58 0u m ( - 8000 , - 670 ) ( - 7780 , - 90 ) 58 0u m 220um ( - 8000 , - 40) ( - 7780 , 5 40 ) 70 um 70 um 70 um ( - 10085,1268) ( - 10155,1198) (10155,1268) (10085,1198) 50 um 20um S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 5 pin configuration com0 com1 com2 com54 com55 com56 : : : : : : : : : : : : segc0 segb0 sega0 segc1 segb1 sega1 segc2 segb2 sega2 : : : : : : : : : : : : : : : : : : : : : : : segc141 segb141 sega141 segc142 segb142 sega142 segc143 segb143 sega143 s6b33b0 (top view) c21m c21p dc2in dc2out vmin vmout v1t v1out v1in c12m c12p c11m c11p vout45 vin45 vin2 vin1(vin1a) vdd1(vdd3=vdd3r) reg_out vdd(vddo) osc1 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 osc2 osc3 osc4 osc5 intrs reg_enb vss db0 rdb wrb rs rstb pm fr cl test0 test1 test2 cs2 cs1b cdir mpu0 mpu1 ps voin c22m c22p c23m c23p c24m c24p c21m vee vrm vrp vcc c31m c31p voin com87 com88 com89 com141 com142 com143 : : : : : : : : : : : : : : : com57 com58 com59 com84 com85 com86 : : : com176 com175 com174 com146 com145 com144 : : : figure 5 . S6B33B0A chip pin configuration 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 6 pad center coordinat es table 2 . pad center coordinates [unit: m m] no x y name no x y name no x y name 1 -9808 -1320 dummy<0> 51 -5308 -1320 vss 101 -808 -1320 vdd3 2 -9718 -1320 dummy<1> 52 -5218 -1320 vss 102 -718 -1320 vdd3 3 -9628 -1320 v0in 53 -5128 -1320 vss 103 -628 -1320 vdd3 4 -9538 -1320 v0in 54 -5038 -1320 vss 104 -538 -1320 vdd3 5 -9448 -1320 v0in 55 -4948 -1320 vssa 105 -448 -1320 vdd3 6 -9358 -1320 v0in 56 -4858 -1320 vssa 106 -358 -1320 vin1 7 -9268 -1320 vss 57 -4768 -1320 vssa 107 -268 -1320 vin1 8 -9178 -1320 ps 58 -4678 -1320 vssa 108 -178 -1320 vin1 9 -9088 -1320 vdd3 59 -4588 -1320 vsso 109 -88 -1320 vin1 10 -8998 -1320 mpu1 60 -4498 -1320 vsso 110 2 -1320 vin1 11 -8908 -1320 vss 61 -4408 -1320 vssb 111 92 -1320 vin1 12 -8818 -1320 mpu0 62 -4318 -1320 vssb 112 182 -1320 vin1 13 -8728 -1320 vdd3 63 -4228 -1320 vssb 113 272 -1320 vin1 14 -8638 -1320 cdir 64 -4138 -1320 vssb 114 362 -1320 vin1 15 -8548 -1320 vss 65 -4048 -1320 vssb 115 452 -1320 vin1 16 -8458 -1320 cs1b 66 -3958 -1320 vssb 116 542 -1320 vin1 17 -8368 -1320 cs2 67 -3868 -1320 vssb 117 632 -1320 vin1 18 -8278 -1320 test2 68 -3778 -1320 vssb 118 722 -1320 vin1a 19 -8188 -1320 test1 69 -3688 -1320 vssb 119 812 -1320 vin1a 20 -8098 -1320 test0 70 -3598 -1320 vssb 120 902 -1320 vin1a 21 -8008 -1320 vdd3 71 -3508 -1320 reg_enb 121 992 -1320 vin1a 22 -7918 -1320 cl 72 -3418 -1320 vdd3 122 1082 -1320 vin2 23 -7828 -1320 fr 73 -3328 -1320 intrs 123 1172 -1320 vin2 24 -7738 -1320 pm 74 -3238 -1320 osc5 124 1262 -1320 vin2 25 -7648 -1320 rstb 75 -3148 -1320 vss 125 1352 -1320 vin2 26 -7558 -1320 rs 76 -3058 -1320 osc4 126 1442 -1320 vin2 27 -7468 -1320 vss 77 -2968 -1320 osc3 127 1532 -1320 vin45 28 -7378 -1320 wrb 78 -2878 -1320 osc2 128 1622 -1320 vin45 29 -7288 -1320 rdb 79 -2788 -1320 osc1 129 1712 -1320 vin45 30 -7198 -1320 vdd3 80 -2698 -1320 vddo 130 1802 -1320 vout45 31 -7108 -1320 db0 81 -2608 -1320 vddo 131 1892 -1320 vout45 32 -7018 -1320 db1 82 -2518 -1320 vdd 132 1982 -1320 vout45 33 -6928 -1320 db2 83 -2428 -1320 vdd 133 2072 -1320 c11p 34 -6838 -1320 db3 84 -2338 -1320 vdd 134 2162 -1320 c11p 35 -6748 -1320 db4 85 -2248 -1320 vdd 135 2252 -1320 c11p 36 -6658 -1320 db5 86 -2158 -1320 vdd 136 2342 -1320 c11m 37 -6568 -1320 db6 87 -2068 -1320 vdd 137 2432 -1320 c11m 38 -6478 -1320 db7 88 -1978 -1320 reg_out 138 2522 -1320 c11m 39 -6388 -1320 db8 89 -1888 -1320 reg_out 139 2612 -1320 c12p 40 -6298 -1320 db9 90 -1798 -1320 reg_out 140 2702 -1320 c12p 41 -6208 -1320 db10 91 -1708 -1320 reg_out 141 2792 -1320 c12p 42 -6118 -1320 db11 92 -1618 -1320 reg_out 142 2882 -1320 c12m 43 -6028 -1320 db12 93 -1528 -1320 reg_out 143 2972 -1320 c12m 44 -5938 -1320 db13 94 -1438 -1320 vdd3r 144 3062 -1320 c12m 45 -5848 -1320 db14 95 -1348 -1320 vdd3r 145 3152 -1320 v1in 46 -5758 -1320 db15 96 -1258 -1320 vdd3r 146 3242 -1320 v1in 47 -5668 -1320 vss 97 -1168 -1320 vdd3r 147 3332 -1320 v1in 48 -5578 -1320 vss 98 -1078 -1320 vdd3r 148 3422 -1320 v1out 49 -5488 -1320 vss 99 -988 -1320 vdd3r 149 3512 -1320 v1out 50 -5398 -1320 vss 100 -898 -1320 vdd3 150 3602 -1320 v1out S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 7 table 2 . pad center coordinates (continued) [unit: m m] no x y name no x y name no x y name 151 3692 -1320 v1t 201 8192 -1320 vcc 251 10120 0 com<30> 152 3782 -1320 v1t 202 8282 -1320 vcc 252 10120 40 com<31> 153 3872 -1320 vmout 203 8372 -1320 vcc 253 10120 80 com<32> 154 3962 -1320 vmout 204 8462 -1320 vrp 254 10120 120 com<33> 155 4052 -1320 vmout 205 8552 -1320 vrp 255 10120 160 com<34> 156 4142 -1320 vmout 206 8642 -1320 vrp 256 10120 200 com<35> 157 4232 -1320 vmin 207 8732 -1320 c31p 257 10120 240 com<36> 158 4322 -1320 vmin 208 8822 -1320 c31p 258 10120 280 com<37> 159 4412 -1320 vmin 209 8912 -1320 c31p 259 10120 320 com<38> 160 4502 -1320 vmin 210 9002 -1320 c31m 260 10120 360 com<39> 161 4592 -1320 dc2out 211 9092 -1320 c31m 261 10120 400 com<40> 162 4682 -1320 dc2out 212 9182 -1320 c31m 262 10120 440 com<41> 163 4772 -1320 dc2out 213 9272 -1320 dummy<4> 263 10120 480 com<42> 164 4862 -1320 dc2in 214 9362 -1320 vss 264 10120 520 com<43> 165 4952 -1320 dc2in 215 9452 -1320 v0in 265 10120 560 com<44> 166 5042 -1320 dc2in 216 9542 -1320 v0in 266 10120 600 com<45> 167 5132 -1320 c21p 217 9632 -1320 v0in 267 10120 640 com<46> 168 5222 -1320 c21p 218 9722 -1320 dummy<5> 268 10120 680 com<47> 169 5312 -1320 c21p 219 9812 -1320 dummy<6> 269 10120 720 com<48> 170 5402 -1320 c21m 220 10120 -1240 dummy<7> 270 10120 760 com<49> 171 5492 -1320 c21m 221 10120 -1200 com<0> 271 10120 800 com<50> 172 5582 -1320 c21m 222 10120 -1160 com<1> 272 10120 840 com<51> 173 5672 -1320 c22p 223 10120 -1120 com<2> 273 10120 880 com<52> 174 5762 -1320 c22p 224 10120 -1080 com<3> 274 10120 920 com<53> 175 5852 -1320 c22p 225 10120 -1040 com<4> 275 10120 960 com<54> 176 5942 -1320 c22m 226 10120 -1000 com<5> 276 10120 1000 com<55> 177 6032 -1320 c22m 227 10120 -960 com<6> 277 10120 1040 com<56> 178 6122 -1320 c22m 228 10120 -920 com<7> 278 10120 1080 dummy<8> 179 6212 -1320 c23p 229 10120 -880 com<8> 279 9960 1233 dummy<9> 180 6302 -1320 c23p 230 10120 -840 com<9> 280 9920 1233 com<57> 181 6392 -1320 c23p 231 10120 -800 com<10> 281 9880 1233 com<58> 182 6482 -1320 c23m 232 10120 -760 com<11> 282 9840 1233 com<59> 183 6572 -1320 c23m 233 10120 -720 com<12> 283 9800 1233 com<60> 184 6662 -1320 c23m 234 10120 -680 com<13> 284 9760 1233 com<61> 185 6752 -1320 c24p 235 10120 -640 com<14> 285 9720 1233 com<62> 186 6842 -1320 c24p 236 10120 -600 com<15> 286 9680 1233 com<63> 187 6932 -1320 c24p 237 10120 -560 com<16> 287 9640 1233 com<64> 188 7022 -1320 c24m 238 10120 -520 com<17> 288 9600 1233 com<65> 189 7112 -1320 c24m 239 10120 -480 com<18> 289 9560 1233 com<66> 190 7202 -1320 c24m 240 10120 -440 com<19> 290 9520 1233 com<67> 191 7292 -1320 vrn 241 10120 -400 com<20> 291 9480 1233 com<68> 192 7382 -1320 vrn 242 10120 -360 com<21> 292 9440 1233 com<69> 193 7472 -1320 vrn 243 10120 -320 com<22> 293 9400 1233 com<70> 194 7562 -1320 vee 244 10120 -280 com<23> 294 9360 1233 com<71> 195 7652 -1320 vee 245 10120 -240 com<24> 295 9320 1233 com<72> 196 7742 -1320 vee 246 10120 -200 com<25> 296 9280 1233 com<73> 197 7832 -1320 vees 247 10120 -160 com<26> 297 9240 1233 com<74> 198 7922 -1320 vees 248 10120 -120 com<27> 298 9200 1233 com<75> 199 8012 -1320 dummy<2> 249 10120 -80 com<28> 299 9160 1233 com<76> 200 8102 -1320 dummy<3> 250 10120 -40 com<29> 300 9120 1233 com<77> 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 8 table 2 . pad center coordinates ( continued) [unit: m m] no x y name no x y name no x y name 301 9080 1233 com<78> 351 7080 1233 segb<13> 401 5080 1233 segc<30> 302 9040 1233 com<79> 352 7040 1233 sega<13> 402 5040 1233 segb<30> 303 9000 1233 com<80> 353 7000 1233 segc<14> 403 5000 1233 sega<30> 304 8960 1233 com<81> 354 6960 1233 segb<14> 404 4960 1233 segc<31> 305 8920 1233 com<82> 355 6920 1233 sega<14> 405 4920 1233 segb<31> 306 8880 1233 com<83> 356 6880 1233 segc<15> 406 4880 1233 sega<31> 307 8840 1233 com<84> 357 6840 1233 segb<15> 407 4840 1233 segc<32> 308 8800 1233 com<85> 358 6800 1233 sega<15> 408 4800 1233 segb<32> 309 8760 1233 com<86> 359 6760 1233 segc<16> 409 4760 1233 sega<32> 310 8720 1233 dummy<10> 360 6720 1233 segb<16> 410 4720 1233 segc<33> 311 8680 1233 segc<0> 361 6680 1233 sega<16> 411 4680 1233 segb<33> 312 8640 1233 segb<0> 362 6640 1233 segc<17> 412 4640 1233 sega<33> 313 8600 1233 sega<0> 363 6600 1233 segb<17> 413 4600 1233 segc<34> 314 8560 1233 segc<1> 364 6560 1233 sega<17> 414 4560 1233 segb<34> 315 8520 1233 segb<1> 365 6520 1233 segc<18> 415 4520 1233 sega<34> 316 8480 1233 sega<1> 366 6480 1233 segb<18> 416 4480 1233 segc<35> 317 8440 1233 segc<2> 367 6440 1233 sega<18> 417 4440 1233 segb<35> 318 8400 1233 segb<2> 368 6400 1233 segc<19> 418 4400 1233 sega<35> 319 8360 1233 sega<2> 369 6360 1233 segb<19> 419 4360 1233 segc<36> 320 8320 1233 segc<3> 370 6320 1233 sega<19> 420 4320 1233 segb<36> 321 8280 1233 segb<3> 371 6280 1233 segc<20> 421 4280 1233 sega<36> 322 8240 1233 sega<3> 372 6240 1233 segb<20> 422 4240 1233 segc<37> 323 8200 1233 segc<4> 373 6200 1233 sega<20> 423 4200 1233 segb<37> 324 8160 1233 segb<4> 374 6160 1233 segc<21> 424 4160 1233 sega<37> 325 8120 1233 sega<4> 375 6120 1233 segb<21> 425 4120 1233 segc<38> 326 8080 1233 segc<5> 376 6080 1233 sega<21> 426 4080 1233 segb<38> 327 8040 1233 segb<5> 377 6040 1233 segc<22> 427 4040 1233 sega<38> 328 8000 1233 sega<5> 378 6000 1233 segb<22> 428 4000 1233 segc<39> 329 7960 1233 segc<6> 379 5960 1233 sega<22> 429 3960 1233 segb<39> 330 7920 1233 segb<6> 380 5920 1233 segc<23> 430 3920 1233 sega<39> 331 7880 1233 sega<6> 381 5880 1233 segb<23> 431 3880 1233 segc<40> 332 7840 1233 segc<7> 382 5840 1233 sega<23> 432 3840 1233 segb<40> 333 7800 1233 segb<7> 383 5800 1233 segc<24> 433 3800 1233 sega<40> 334 7760 1233 sega<7> 384 5760 1233 segb<24> 434 3760 1233 segc<41> 335 7720 1233 segc<8> 385 5720 1233 sega<24> 435 3720 1233 segb<41> 336 7680 1233 segb<8> 386 5680 1233 segc<25> 436 3680 1233 sega<41> 337 7640 1233 sega<8> 387 5640 1233 segb<25> 437 3640 1233 segc<42> 338 7600 1233 segc<9> 388 5600 1233 sega<25> 438 3600 1233 segb<42> 339 7560 1233 segb<9> 389 5560 1233 segc<26> 439 3560 1233 sega<42> 340 7520 1233 sega<9> 390 5520 1233 segb<26> 440 3520 1233 segc<43> 341 7480 1233 segc<10> 391 5480 1233 sega<26> 441 3480 1233 segb<43> 342 7440 1233 segb<10> 392 5440 1233 segc<27> 442 3440 1233 sega<43> 343 7400 1233 sega<10> 393 5400 1233 segb<27> 443 3400 1233 segc<44> 344 7360 1233 segc<11> 394 5360 1233 sega<27> 444 3360 1233 segb<44> 345 7320 1233 segb<11> 395 5320 1233 segc<28> 445 3320 1233 sega<44> 346 7280 1233 sega<11> 396 5280 1233 segb<28> 446 3280 1233 segc<45> 347 7240 1233 segc<12> 397 5240 1233 sega<28> 447 3240 1233 segb<45> 348 7200 1233 segb<12> 398 5200 1233 segc<29> 448 3200 1233 sega<45> 349 7160 1233 sega<12> 399 5160 1233 segb<29> 449 3160 1233 segc<46> 350 7120 1233 segc<13> 400 5120 1233 sega<29> 450 3120 1233 segb<46> S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 9 table 2 . pad center coordinates (continued) [unit: m m] no x y name no x y name no x y name 451 3080 1233 sega<46> 501 1080 1233 segb<63> 551 -920 1233 segc<80> 452 3040 1233 segc<47> 502 1040 1233 sega<63> 552 -960 1233 segb<80> 453 3000 1233 segb<47> 503 1000 1233 segc<64> 553 -1000 1233 sega<80> 454 2960 1233 sega<47> 504 960 1233 segb<64> 554 -1040 1233 segc<81> 455 2920 1233 segc<48> 505 920 1233 sega<64> 555 -1080 1233 segb<81> 456 2880 1233 segb<48> 506 880 1233 segc<65> 556 -1120 1233 sega<81> 457 2840 1233 sega<48> 507 840 1233 segb<65> 557 -1160 1233 segc<82> 458 2800 1233 segc<49> 508 800 1233 sega<65> 558 -1200 1233 segb<82> 459 2760 1233 segb<49> 509 760 1233 segc<66> 559 -1240 1233 sega<82> 460 2720 1233 sega<49> 510 720 1233 segb<66> 560 -1280 1233 segc<83> 461 2680 1233 segc<50> 511 680 1233 sega<66> 561 -1320 1233 segb<83> 462 2640 1233 segb<50> 512 640 1233 segc<67> 562 -1360 1233 sega<83> 463 2600 1233 sega<50> 513 600 1233 segb<67> 563 -1400 1233 segc<84> 464 2560 1233 segc<51> 514 560 1233 sega<67> 564 -1440 1233 segb<84> 465 2520 1233 segb<51> 515 520 1233 segc<68> 565 -1480 1233 sega<84> 466 2480 1233 sega<51> 516 480 1233 segb<68> 566 -1520 1233 segc<85> 467 2440 1233 segc<52> 517 440 1233 sega<68> 567 -1560 1233 segb<85> 468 2400 1233 segb<52> 518 400 1233 segc<69> 568 -1600 1233 sega<85> 469 2360 1233 sega<52> 519 360 1233 segb<69> 569 -1640 1233 segc<86> 470 2320 1233 segc<53> 520 320 1233 sega<69> 570 -1680 1233 segb<86> 471 2280 1233 segb<53> 521 280 1233 segc<70> 571 -1720 1233 sega<86> 472 2240 1233 sega<53> 522 240 1233 segb<70> 572 -1760 1233 segc<87> 473 2200 1233 segc<54> 523 200 1233 sega<70> 573 -1800 1233 segb<87> 474 2160 1233 segb<54> 524 160 1233 segc<71> 574 -1840 1233 sega<87> 475 2120 1233 sega<54> 525 120 1233 segb<71> 575 -1880 1233 segc<88> 476 2080 1233 segc<55> 526 80 1233 sega<71> 576 -1920 1233 segb<88> 477 2040 1233 segb<55> 527 40 1233 segc<72> 577 -1960 1233 sega<88> 478 2000 1233 sega<55> 528 0 1233 segb<72> 578 -2000 1233 segc<89> 479 1960 1233 segc<56> 529 -40 1233 sega<72> 579 -2040 1233 segb<89> 480 1920 1233 segb<56> 530 -80 1233 segc<73> 580 -2080 1233 sega<89> 481 1880 1233 sega<56> 531 -120 1233 segb<73> 581 -2120 1233 segc<90> 482 1840 1233 segc<57> 532 -160 1233 sega<73> 582 -2160 1233 segb<90> 483 1800 1233 segb<57> 533 -200 1233 segc<74> 583 -2200 1233 sega<90> 484 1760 1233 sega<57> 534 -240 1233 segb<74> 584 -2240 1233 segc<91> 485 1720 1233 segc<58> 535 -280 1233 sega<74> 585 -2280 1233 segb<91> 486 1680 1233 segb<58> 536 -320 1233 segc<75> 586 -2320 1233 sega<91> 487 1640 1233 sega<58> 537 -360 1233 segb<75> 587 -2360 1233 segc<92> 488 1600 1233 segc<59> 538 -400 1233 sega<75> 588 -2400 1233 segb<92> 489 1560 1233 segb<59> 539 -440 1233 segc<76> 589 -2440 1233 sega<92> 490 1520 1233 sega<59> 540 -480 1233 segb<76> 590 -2480 1233 segc<93> 491 1480 1233 segc<60> 541 -520 1233 sega<76> 591 -2520 1233 segb<93> 492 1440 1233 segb<60> 542 -560 1233 segc<77> 592 -2560 1233 sega<93> 493 1400 1233 sega<60> 543 -600 1233 segb<77> 593 -2600 1233 segc<94> 494 1360 1233 segc<61> 544 -640 1233 sega<77> 594 -2640 1233 segb<94> 495 1320 1233 segb<61> 545 -680 1233 segc<78> 595 -2680 1233 sega<94> 496 1280 1233 sega<61> 546 -720 1233 segb<78> 596 -2720 1233 segc<95> 497 1240 1233 segc<62> 547 -760 1233 sega<78> 597 -2760 1233 segb<95> 498 1200 1233 segb<62> 548 -800 1233 segc<79> 598 -2800 1233 sega<95> 499 1160 1233 sega<62> 549 -840 1233 segb<79> 599 -2840 1233 segc<96> 500 1120 1233 segc<63> 550 -880 1233 sega<79> 600 -2880 1233 segb<96> 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 10 table 2 . pad center coordinates (continued) [unit: m m] no x y name no x y name no x y name 601 -2920 1233 sega<96> 651 -4920 1233 segb<113> 701 -6920 1233 segc<130> 602 -2960 1233 segc<97> 652 -4960 1233 sega<113> 702 -6960 1233 segb<130> 603 -3000 1233 segb<97> 653 -5000 1233 segc<114> 703 -7000 1233 sega<130> 604 -3040 1233 sega<97> 654 -5040 1233 segb<114> 704 -7040 1233 segc<131> 605 -3080 1233 segc<98> 655 -5080 1233 sega<114> 705 -7080 1233 segb<131> 606 -3120 1233 segb<98> 656 -5120 1233 segc<115> 706 -7120 1233 sega<131> 607 -3160 1233 sega<98> 657 -5160 1233 segb<115> 707 -7160 1233 segc<132> 608 -3200 1233 segc<99> 658 -5200 1233 sega<115> 708 -7200 1233 segb<132> 609 -3240 1233 segb<99> 659 -5240 1233 segc<116> 709 -7240 1233 sega<132> 610 -3280 1233 sega<99> 660 -5280 1233 segb<116> 710 -7280 1233 segc<133> 611 -3320 1233 segc<100> 661 -5320 1233 sega<116> 711 -7320 1233 segb<133> 612 -3360 1233 segb<100> 662 -5360 1233 segc<117> 712 -7360 1233 sega<133> 613 -3400 1233 sega<100> 663 -5400 1233 segb<117> 713 -7400 1233 segc<134> 614 -3440 1233 segc<101> 664 -5440 1233 sega<117> 714 -7440 1233 segb<134> 615 -3480 1233 segb<101> 665 -5480 1233 segc<118> 715 -7480 1233 sega<134> 616 -3520 1233 sega<101> 666 -5520 1233 segb<118> 716 -7520 1233 segc<135> 617 -3560 1233 segc<102> 667 -5560 1233 sega<118> 717 -7560 1233 segb<135> 618 -3600 1233 segb<102> 668 -5600 1233 segc<119> 718 -7600 1233 sega<135> 619 -3640 1233 sega<102> 669 -5640 1233 segb<119> 719 -7640 1233 segc<136> 620 -3680 1233 segc<103> 670 -5680 1233 sega<119> 720 -7680 1233 segb<136> 621 -3720 1233 segb<103> 671 -5720 1233 segc<120> 721 -7720 1233 sega<136> 622 -3760 1233 sega<103> 672 -5760 1233 segb<120> 722 -7760 1233 segc<137> 623 -3800 1233 segc<104> 673 -5800 1233 sega<120> 723 -7800 1233 segb<137> 624 -3840 1233 segb<104> 674 -5840 1233 segc<121> 724 -7840 1233 sega<137> 625 -3880 1233 sega<104> 675 -5880 1233 segb<121> 725 -7880 1233 segc<138> 626 -3920 1233 segc<105> 676 -5920 1233 sega<121> 726 -7920 1233 segb<138> 627 -3960 1233 segb<105> 677 -5960 1233 segc<122> 727 -7960 1233 sega<138> 628 -4000 1233 sega<105> 678 -6000 1233 segb<122> 728 -8000 1233 segc<139> 629 -4040 1233 segc<106> 679 -6040 1233 sega<122> 729 -8040 1233 segb<139> 630 -4080 1233 segb<106> 680 -6080 1233 segc<123> 730 -8080 1233 sega<139> 631 -4120 1233 sega<106> 681 -6120 1233 segb<123> 731 -8120 1233 segc<140> 632 -4160 1233 segc<107> 682 -6160 1233 sega<123> 732 -8160 1233 segb<140> 633 -4200 1233 segb<107> 683 -6200 1233 segc<124> 733 -8200 1233 sega<140> 634 -4240 1233 sega<107> 684 -6240 1233 segb<124> 734 -8240 1233 segc<141> 635 -4280 1233 segc<108> 685 -6280 1233 sega<124> 735 -8280 1233 segb<141> 636 -4320 1233 segb<108> 686 -6320 1233 segc<125> 736 -8320 1233 sega<141> 637 -4360 1233 sega<108> 687 -6360 1233 segb<125> 737 -8360 1233 segc<142> 638 -4400 1233 segc<109> 688 -6400 1233 sega<125> 738 -8400 1233 segb<142> 639 -4440 1233 segb<109> 689 -6440 1233 segc<126> 739 -8440 1233 sega<142> 640 -4480 1233 sega<109> 690 -6480 1233 segb<126> 740 -8480 1233 segc<143> 641 -4520 1233 segc<110> 691 -6520 1233 sega<126> 741 -8520 1233 segb<143> 642 -4560 1233 segb<110> 692 -6560 1233 segc<127> 742 -8560 1233 sega<143> 643 -4600 1233 sega<110> 693 -6600 1233 segb<127> 743 -8600 1233 dummy<11> 644 -4640 1233 segc<111> 694 -6640 1233 sega<127> 744 -8640 1233 com<176> 645 -4680 1233 segb<111> 695 -6680 1233 segc<128> 745 -8680 1233 com<175> 646 -4720 1233 sega<111> 696 -6720 1233 segb<128> 746 -8720 1233 com<174> 647 -4760 1233 segc<112> 697 -6760 1233 sega<128> 747 -8760 1233 com<173> 648 -4800 1233 segb<112> 698 -6800 1233 segc<129> 748 -8800 1233 com<172> 649 -4840 1233 sega<112> 699 -6840 1233 segb<129> 749 -8840 1233 com<171> 650 -4880 1233 segc<113> 700 -6880 1233 sega<129> 750 -8880 1233 com<170> S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 11 table 2 . pad center coordinates (continued) [unit: m m] no x y name no x y name 751 -8920 1233 com<169> 801 -10120 160 com<121> 752 -8960 1233 com<168> 802 -10120 120 com<120> 753 -9000 1233 com<167> 803 -10120 80 com<119> 754 -9040 1233 com<166> 804 -10120 40 com<118> 755 -9080 1233 com<165> 805 -10120 0 com<117> 756 -9120 1233 com<164> 806 -10120 -40 com<116> 757 -9160 1233 com<163> 807 -10120 -80 com<115> 758 -9200 1233 com<162> 808 -10120 -120 com<114> 759 -9240 1233 com<161> 809 -10120 -160 com<113> 760 -9280 1233 com<160> 810 -10120 -200 com<112> 761 -9320 1233 com<159> 811 -10120 -240 com<111> 762 -9360 1233 com<158> 812 -10120 -280 com<110> 763 -9400 1233 com<157> 813 -10120 -320 com<109> 764 -9440 1233 com<156> 814 -10120 -360 com<108> 765 -9480 1233 com<155> 815 -10120 -400 com<107> 766 -9520 1233 com<154> 816 -10120 -440 com<106> 767 -9560 1233 com<153> 817 -10120 -480 com<105> 768 -9600 1233 com<152> 818 -10120 -520 com<104> 769 -9640 1233 com<151> 819 -10120 -560 com<103> 770 -9680 1233 com<150> 820 -10120 -600 com<102> 771 -9720 1233 com<149> 821 -10120 -640 com<101> 772 -9760 1233 com<148> 822 -10120 -680 com<100> 773 -9800 1233 com<147> 823 -10120 -720 com<99> 774 -9840 1233 com<146> 824 -10120 -760 com<98> 775 -9880 1233 com<145> 825 -10120 -800 com<97> 776 -9920 1233 com<144> 826 -10120 -840 com<96> 777 -9960 1233 dummy<12> 827 -10120 -880 com<95> 778 -10120 1080 dummy<13> 828 -10120 -920 com<94> 779 -10120 1040 com<143> 829 -10120 -960 com<93> 780 -10120 1000 com<142> 830 -10120 -1000 com<92> 781 -10120 960 com<141> 831 -10120 -1040 com<91> 782 -10120 920 com<140> 832 -10120 -1080 com<90> 783 -10120 880 com<139> 833 -10120 -1120 com<89> 784 -10120 840 com<138> 834 -10120 -1160 com<88> 785 -10120 800 com<137> 835 -10120 -1200 com<87> 786 -10120 760 com<136> 836 -10120 -1240 dummy<14> 787 -10120 720 com<135> 788 -10120 680 com<134> 789 -10120 640 com<133> 790 -10120 600 com<132> 791 -10120 560 com<131> 792 -10120 520 com<130> 793 -10120 480 com<129> 794 -10120 440 com<128> 795 -10120 400 com<127> 796 -10120 360 com<126> 797 -10120 320 com<125> 798 -10120 280 com<124> 799 -10120 240 com<123> 800 -10120 200 com<122> 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 12 pin description table 3 . power s upply p ins name i/o description vdd 3 supply main p ower su pply vdd3r supply internal regulator power supply this pin is connected to vdd3. vdd supply regulated power supply input pin for internal digital and ddram block. this pin is connected to reg_out outside the chip with stabilization capacitor. when the in ternal regulator is not used, vdd1 should be tied to vdd directly. vddo supply internal oscillator power supply this pin is connected to vdd. v ss vsso vssa vssb gnd ground v1in i lcd segment high selected driving voltage input pin v1out o lcd segment h igh driving voltage output pin vmin i lcd common/segment non - selected driving voltage input pin vmout o lcd common/segment non - selected driving voltage output pin v0in i lcd segment low selected driving voltage input pin vcc i lcd common high selected driving voltage input pin vrp o lcd common high selected driving voltage output pin vee vees i lcd common low selected driving voltage input pin the relationship between vcc, v1, vm, v0 and vee: vcc > v1 > vm > v0(=vss) > vee (v1 - vm = vm ? v0, vcc ? vm = vm - vee) vrn o lcd common low selected driving voltage output pin vin1 vin1a i power supply for 1 ? st booster circuit and vm amp vin2 i power supply for 2 ? nd booster circuit vout45 o 1 ? st booster output pin vin45 i power supply for v1. connect to v out45 or vin1 c11p c11m c12p c12m o external capacitor connection pins used for 1 ? st booster circuit v1t i thermistor resistor connection pin intrs i external resister select pin for temperature compensation circuit - intrs = l : external resistor mode, intrs = h : internal resistor mode dc2in i power supply for 2 ? nd booster. connect to dc2out pin dc2out o power output pin for 2 ? nd booster input c21p c21m c22p c22m c23p c23m c24p c24m o external capacitor connection pins used for 2 ? nd booster circuit c31p c31m o external capacitor connection pins used for 3 ? rd booster circuit S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 13 table 4 . mpu interface p ins name i/o description rstb i reset input pin . when rs t b is ?l?, initialization is executed. mpu interface se lect pin ps mpu[1] mpu[0] description h l l 8080 - series 8bit interface h l h 8080 - series 16bit interface h h l 6800 - series 8bit interface h h h 6800 - series 16bit interface l l x 3 pin spi(write only) ps mpu[1:0] i l h x 4 pin spi(write only) cs1 b c s2 i chip select input pins data / instruction i/o is enabled only when cs1 b is ?l? and cs2 is ?h?. when chip select is non - active, db0 to db 15 may be high impedance. d/i (rs) i data / instruction select input pin - d/i = ?h?: db0 to db 15 are display dat a - d/i = ?l?: db 0 to db 7 are instruction data read / write execution control pin ps mpu mpu type wrb description h h 6800 - series r / w readwrbite control input pin - r / w = ?h?: read - r / w = ?l?: write wr b (r/w) i h l 8080 - series wr b write enable c lock input pin the data on db0 to db 15 are latched at the rising edge of the wr b signal. read / write execution control pin mpu [1] mpu t ype rd b description h 6800 - series e read / write control input pin - r / w = ?h?: when e is ?h?, db0 to d b 15 are in an output status. - r / w = ?l?: the data on db0 to db 15 are latched at the falling edge of the e signal. rdb (e) i l 8080 - series rd b read enable clock input pin when rd b is ?l?, db0 to db 15 are in an output status. db[15:8] db[7]/sdi db[6]/scl db[ 5:0] i/o - db[15:0]: 16 - bit bi - directional data bus . - sdi: serial data input pin. the data is latched at the rising edge of scl. - scl: serial clock input pin. cdir i common direction select pin. 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 14 table 5. oscillator and power regulator p ins name i/o desc ription osc1 osc2 osc3 osc4 o cr oscillator output pin when the internal cr oscillator is used, connect to osc1, osc3 through a resistor. osc1 ? osc2: using in normal display mode, partial display mode 0 osc3 ? osc4: using in partial display mode 1 when a n external oscillator is used, osc1 pin is connected to vdd or vss. osc5 i external clock input pin when an external input is used, it is input to this pin. but the internal oscillator is used, this pin is connected to vdd or vss. reg_enb i internal reg ulator enable/disable input pin - reg_enb = ? l ? (tied to vss) : enable internal regulator - reg_enb = ? h ? (tied to vdd) : disable internal regulator reg_out o internal voltage regulator output pin the regulator output port from this pin is used as a power supplier for an internal digital block via vdd pins. table 6. timing signal pins for monitoring name i/o description cl o shift clock output pin pm o field delimiter output pin fr o liquid crystal alternating current output pin table 7. lcd driver output pins name i/o description sega0 to 143 o lcd driving segment output (red or blue) segb0 to 143 o lcd driving segment output (green) segc0 to143 o lcd driving segment output (blue or red) com0 to 176 o lcd common outputs table 8. test pins nam e i/o description test[2:0] i don ? t use these pins. ic maker ? s test pins these pins must be tied to vdd. S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 15 functional descripti on m pu interface chip select input there are cs1b and cs2 pins for c hip s election. the S6B33B0A can interface with an mpu only when cs1b is ?l? and cs2 is ?h?. when these pins are set to any other combination, d/i, rdb, and wrb inputs are disabled and db0 to db 15 are to be high impedance . and, in case of serial interface, the internal shift register and the counter are reset. pa rallel/serial interface the S6B33B0A has four types of interface with an mpu, which are two serial and two parallel interfaces. this parallel or serial interface is determined by ps pin as shown in table9. table 9. parallel / serial interface mode. ps mp u[1] cs1b cs2 mpu bus type l 8080 - series mpu h h cs1b cs2 6800 - series mpu l 3 ? pin spi l h cs1b cs2 4 - pin spi parallel interface (ps= ? h ? ) the 8 - bit /16 - bit bi - directional data bus is used in parallel interface . the type of mpu is sele cted by mpu [1] and the mode of data - bus is controlled by mpu[0] as shown in below. in accessing internal registers ( d/i = ? l ? ), only db[7:0] are valid. table 10. microprocessor selection for parallel interface mpu[1] mpu[0] cs1b cs2 rdb wrb data bus mpu bu s type l db[7:0] l h cs1b cs2 rdb w rb db[15:0 ] 8080 - series mpu l db[7:0] h h cs1b cs2 e r/w db[15:0] 6800 - series mpu table 11. parallel data transfer 6800 - series 8080 - series d/i rdb wrb rdb wrb description h h h l h read d isplay data h h l h l write d isplay data l h h l h read out internal status r egister l h l h l write instruction data 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 16 / cs1 cs2 d/i r/w e db command write data w rite status read data read figure 6. 6800 - series mpu interface protocol (mpu[1]= ? h ? ) / cs1 cs2 d/i /wr /rd db command write data w rite status read data read fig ure 7. 8080 - series mpu interface protocol (mpu[1]= ? l ? ) S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 17 serial interface(ps= ? l ? ) communication with the microprocessor occurs via a clock - synchronized serial peripheral interface when ps is low. when using the serial interface, read operations are not a llowed. when the chip select inputs are valid (cs1b = ? l ? & cs2 = ? h ? ) , the s erial data is sent most significant bit first on the rising edge of a serial clock going into db6 and processed as 8 bit parallel data on the eighth clock . since the clock signal is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended . and invalid , the internal shift register and the counter are reset. t he serial interface type is selected by setting ps as sh own in table12. t able 12. microprocessor selection for serial interface ps mpu[1] cs1b cs2 d/i serial data serial clock spi mode l cs1b cs2 by s/w 3 - pin l h cs1b cs2 d/i db[7] db[6] 4 - pin 3 - pin sp i interface ( ps = " l " & mpu[1] = " l ") in 3 - pin spi interface mode, the pre - defined instruction called display data length is used to indicate whether serial data input is display or instruction data instead of d/i pin. the data is handled as instruction d ata until the display data length instruction is issued. this display data length instruction consists of three bytes instruction. the first byte instruction enables the next instruction to be valid, and data of the second two bytes indicate that a specifi ed number of display data bytes(1 to 65536) are to be transmitted. next two bytes after the display data string is handled as instruction data. for details, refer the figure 8. chip select scl(db6) sdi(db7) internal d/i /cs1 = l, cs2 = h 1 24 ddl_h ddl_l 2 23 1 2 160 159 10 pixel display data ddl_l = 09h user's display data (max. 50688(176x144) bytes) 20 bytes(2) 3 bytes (1) ddc ddl_h = 00h ddl = 0009h(9d) (1) set ddc(display data command) and ddl(display data length) set ddc(3 pin spi mode only) : 1 1 1 1 1 1 0 0 (fch) set ddl(2 bytes) : (1'st byte) d7 d6 d5 d4 d3 d2 d1 d0 (ddl_l) (2'nd byte) d7 d6 d5 d4 d3 d2 d1 d0 (ddl_h) (2) ddl register value number of display data : (ddl + 1) pixel data ((ddl+1) x 2 byte) necessary clock pulse number : 8 x [(ddl+1) x 2] figure 8. 3 - pin spi timing (d/i is not used) 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 18 4 - p in serial interface (ps= ? l ? & mpu[1]= ? h ? ) in 4 - pin spi interface mode, d/i pin is used for indicating whether serial data input is display or instruction data. d ata is display data when d/i is high and instruction data when d/i is low. serial data can be r ead on the rising edge of serial clock going into db6 and processed as 8 - bit parallel data on the eighth serial clock. l chip select sid (db7) scl (db6) d/i db0 db1 db 4 db 6 db 7 db 3 /cs1=l, cs2=h db5 db2 db 7 db 6 figure 9. 4 - pin serial interface timing S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 19 display data ram the on - chip display data ram of S6B33B0A is a stat ic ram that is stored the data for the display. it is a 2,304 x 176 structure. it is controlled by 2 addresses, x and y. and, ram area selection and automatic address count up functions are accomplished by the internal instructions. ddram address area se lection a part of ddram address area of S6B33B0A can be accessed by x and y address area settings . after setting ram area , the address es become the start address. x-address area y-address area figure 10 . ddram address area table 13. x address c ontrol db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 1 0 0 0 0 1 p1 x start address set(initial status = 00h) p2 x end address set(initial status = afh) table 14. y address c ontrol db7 db6 db5 db4 db3 db2 db1 db0 code 0 0 1 1 0 0 0 1 p1 y start address set (init ial status = 00h) p2 y end address set (initial status =8fh) 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 20 ram addressing count up by selecting the x address and y address area by the internal instructions , the address counts up from its start address to end address after data access operation . w hen one address is equal to the end address, it returns to the start address. at this time, the other address is increased by 1 . y address count mode (y address = 00h to 8f h, x address = 00h to af h) y- address 1 2 3 4 5 6 7 8 9 00 h 01 h 02 h 03 h 04 h 05 h 07 h 08 h 06 h x- address 00h 01h 02h 03h af h 145 289 25201 144 8fh 288 432 576 25344 433 figure 11 . y a ddress c ount m ode x address count mode (y address = 0 0h to 8f h, x address = 00h to af h) y- address 1 177 324 486 648 810 972 1134 1296 21222 00h 01h 02h 03h 04h 05h 8f h 07h 08h 06h x- address 00h 01h 02h 03h af h 2 3 4 176 352 528 704 880 1056 1232 1408 1584 25344 figure 12 . x address count mode S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 21 xa address ya address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 00h 01h 02h 03h 04h 05h 06h 07h 89h 8ah 8bh 8ch 8dh 8eh 8fh 08h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - a0h a1h a2h a3h a4h a5h a6h a7h a8h a9h aah abh ach adh aeh afh - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 red green blue figure 13 . display data ram map 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 22 partial display mode the S6B33B0A realizes the partial dis play function with low duty driving for saving power consumption and showing the various display duties. it is set as display start/end line number. area scroll function the S6B33B0A realizes the specific area scroll function. (1/ 176 duty case). 0 15 161 175 fixed area scroll area display area lcd panel fixed 15 lines 146 lines 14 fixed 15 lines 0 160 161 175 14 example of scrolling down e xample of scrolling up 15 figure 14. area scroll examples (duty = 1/176, center scroll mode) S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 23 display direction sdir the sdir flag of driver output mode set instruction selects the direction of segment display . x = 0 y = 1 y = 143 y = 0 sega0 segb0 segc0 sega1 segb1 segc1 sega1 43 segb1 43 segc1 43 (d7~d0) (d 7 ~d0) (d 7 ~d0) (d7~d0) (d7~d0) (d 7 ~d0) 1st 2nd f igure 15. 8 - bit data bus mode when sdir = l y = 1 y = 1 43 y = 0 sega0 segb0 segc0 sega1 segb1 segc1 sega1 43 segb1 43 segc1 43 (d1 5 ~d0) (d1 5 ~d0) (d1 5 ~d0) x=0 figure 16. 16 - bit data bus mode when sdir = l x = 0 y = 1 42 y = 0 y = 1 43 sega0 segb0 segc0 sega1 segb1 segc1 sega1 43 segb1 43 1 segc1 43 (d7~d0) (d 7 ~d0) (d 7 ~d0) (d7~d0) (d7~d0) (d 7 ~d0) 1st 2nd figure 17. 8 - bit data bus mode when sdir = h y = 142 y = 0 y = 1 43 sega0 segb0 segc0 sega1 segb1 segc1 sega1 43 segb1 43 segc1 43 (d1 5 ~d0) (d1 5 ~d0) (d1 5 ~d0) x = 0 figure 18. 16 - bit data bus mode when sdir = h 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 24 cdir the direction of common scanning is selected by cdir pin. com 0 com 62 line number 0 line number 62 line number 63 display area 128 display lines (dln=00) S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 25 swp the swp flag of driver output mode set instruction selects the swapping of segment display . segai segbi segci red green blue color swp = 0 d15 ~ d11 d10~ d5 d4 ~ d0 assigned bit blue green red color swp = 1 d4~ d0 d10 ~ d5 d15 ~ d11 assigned bit figure 19. the relationship between seg output s and rgb color swp=1 * i = 0 to 1 43 r control b control g control d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 ram data swp=0 * i = 0 to 1 43 b contro l r control g control segai segbi segci d 4 d 3 d 1 d 0 d 9 d 8 d 7 d 5 d 15 d1 4 d 13 d 11 mpu i/f data ram data mpu i/f data segai segbi segci d2 d13 d 10 d 6 d 12 d10 d7 d1 d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 d13 d10 d7 d1 d15 d14 d12 d11 d9 d8 d6 d5 d4 d3 d2 d0 d13 d10 d7 d1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 26 on - chip regulato r configuration the output voltage of regulator circuit (reg_out) is ranging from 1.8v to 2.2v and nominal value is 1.8v. reg_enb reg_out vdd /vddo vdd 3 /vdd3r c1 vdd 3 reg_enb reg_out floating vdd 3 vdd 3 value of external capacitance item value unit c1 1.0 to 4.7 m f vdd3: 2.4 to 3.3v reg_out : 1.8v vdd3: 1.8 to 3.3v vdd /vddo vdd 3 /vdd3r figure 20 . regulator application oscillator circuit when internal oscillator is used(ext=0), the selection of oscillator resistor is determined by display mode . - normal display mode/ part ial display mode 0 : resistor1 between osc1 and osc2 - partial display mode 1 : resistor2 between osc3 and osc4 when external clock is used ( ext=1), clock frequency should be adjusted to display mode which is selected . example of external oscillator applic ation osc4 osc2 osc3 osc5 external clock osc1 vss figure 21. external oscillator application S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 27 example of internal oscillator application osc4 osc2 osc3 r1 osc5 vss/vdd3 osc1 osc4 osc2 osc3 osc5 osc1 vss/vdd3 r2 r1 when partial display mode 1 is not used. when partial display mode 1 is used. figure 22. internal oscillator application discharge circuit driving voltage level discharge time at standby on. the relation between voltage level and discharge time from when ? standby on ? command is inputted. level condition t[ms] d v+, d v - [mv] 100 < 50 +vr,v1,vm, - v r +vr=12.0v, v1=3.0v, vm=1.5v, - vr= - 9.0v at t=0 300 < 20 vm vss -vr v1 +vr internal stb signal t[ms] v+[mv] v-[mv] 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 28 instruction description table 15 . instruction table instruction name d/i wrb rdb db15 ~ db8 db7 db6 db5 db4 db3 db2 db1 db0 hex. parameter non operation 0 0 1 * 0 0 0 0 0 0 0 0 00 oscillation mode set 0 0 1 * 0 0 0 0 0 0 1 0 02 1byte driver output mode set 0 0 1 * 0 0 0 1 0 0 0 0 10 1byte dc - dc select 0 0 1 * 0 0 1 0 0 0 0 0 20 1byte bias set 0 0 1 * 0 0 1 0 0 0 1 0 22 1byte dcdc clock division set 0 0 1 * 0 0 1 0 0 1 0 0 24 1by te dcdc and amp on/off set 0 0 1 * 0 0 1 0 0 1 1 0 26 1byte temperature compensation set 0 0 1 * 0 0 1 0 1 0 0 0 28 1byte contrast control(1) 0 0 1 * 0 0 1 0 1 0 1 0 2a 1byte contrast control(2) 0 0 1 * 0 0 1 0 1 0 1 1 2b 1byte standby mode off 0 0 1 * 0 0 1 0 1 1 0 0 2c - standby mode on 0 0 1 * 0 0 1 0 1 1 0 1 2d - ddram burst mode off 0 0 1 * 0 0 1 0 1 1 1 0 2e - ddram burst mode on 0 0 1 * 0 0 1 0 1 1 1 1 2f - addressing mode set 0 0 1 * 0 0 1 1 0 0 0 0 30 1byte row vector mode set 0 0 1 * 0 0 1 1 0 0 1 0 32 1byte n - line inversion set 0 0 1 * 0 0 1 1 0 1 0 0 34 1byte entry mode set 0 0 1 * 0 1 0 0 0 0 0 0 40 1byte x - address area set 0 0 1 * 0 1 0 0 0 0 1 0 42 2byte y - address area set 0 0 1 * 0 1 0 0 0 0 1 1 43 2byte ram skip area set 0 0 1 * 0 1 0 0 0 1 0 1 45 1byte display off 0 0 1 * 0 1 0 1 0 0 0 0 50 - display on 0 0 1 * 0 1 0 1 0 0 0 1 51 - specified display pattern set 0 0 1 * 0 1 0 1 0 0 1 1 53 1byte partial display mode set 0 0 1 * 0 1 0 1 0 1 0 1 55 1byte partial display st art line set 0 0 1 * 0 1 0 1 0 1 1 0 56 1byte partial display end line set 0 0 1 * 0 1 0 1 0 1 1 1 57 1byte area scroll mode set 0 0 1 * 0 1 0 1 1 0 0 1 59 4byte scroll start line set 0 0 1 * 0 1 0 1 1 0 1 0 5a 1byte set display data length x x x * 1 1 1 1 1 1 0 0 fc 1byte display data write 1 0 1 display data write - - display data read 1 1 0 display data read - - status read 0 1 0 0 status data read - - test mode1 0 0 1 * 1 1 1 1 1 1 1 1 ff - test mode2 0 0 1 * 1 1 1 1 1 1 1 0 fe - test mode3 0 0 1 * 1 1 1 1 1 1 0 1 fd - test mode4 0 0 1 * 1 1 1 1 1 0 1 1 fb - test mode5 0 0 1 * 1 1 1 1 1 0 1 0 fa - test mode6 0 0 1 * 1 1 1 1 1 0 0 1 f9 - *: don ? t care parameter: the number of parameter bytes that follows instruction data. S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 29 non operation (00h ) this instruction is non operation . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 0 0 oscillation mode set (02h) setting internal function mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ext osc ext: external clock selecting ext = 0: internal clock mode (initial status) ext = 1: external clock mode osc: internal oscillator on/off osc = 0: internal oscillator off(initial status) osc = 1: internal oscillator on driver output mode set(10h ) this instruction sets the display direction. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 0 0 1 0 0 dln 0 sdir swp 0 dln: display line number selecting db 5 db 4 display duty 0 0 1/128 0 1 1/144 1 0 1/160 1 1 1/176 sdir: segment direction this bit is for controlling the direction of segment driver. sdir = 0 (initial status) swp: swap segment output segai and segci this bit is for swapping the output of segment driver. swp = 0 (initial status) 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 30 dc - dc select (20h) selects dc - dc step - up of the common driver in normal and partial mode d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 dc(2) dc(1) dc(1) : 1 ? st dc - dc booster boosting step select for v1 generation in normal mode and pa rtial mode 0. dc(2) : 1 ? st dc - dc booster boosting step select for v1 generation in partial mode 1. dc(2) : in partial mode 1 dc ( 1 ) : in normal mode, partial mode 0 db 3 db2 dc - dc step up db 1 db0 dc - dc step up 0 0 x1.0 0 0 x1.0 0 1 x1.5 0 1 x1.5 1 0 x2.0 1 0 x2.0 1 1 x2.0 1 1 x2.0 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 31 dc - dc select and power supply for v1 op - amp. even if vin45 is connected to vout45 or vin1, a setup by software must be able to be performed. power supply for v1 op.amp. is decided by hardware setting and software setting. the example of usage is shown below. hardware setting : vin45 connected to (1) vin1 (when 1 ? st boosting is not used) (2) vout45 (when 1 ? s t boosting is used) software setting : dc - dc select(20h) - dc(1), dc(2) set value ? 00 ? power supply for v1 op.amp. uses vin1 directly. set value ? 01 ? or ? 10 ? power supply for v1 o p.amp. uses vout45. 1st booster circuit reference voltage generator & temperature compensation control circuit vin1 v1 + c11- c11+ c12- c12+ vout45 vin45 - r1 ev_256 r1 software setting hardware setting v1 generation circuit figure28. example : hardware setting software setting : vin45 connected to vout45 : power supply for v1 op.amp. uses vin1 ( not vout45). vss 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 32 bias set (22h) this instruction set up the value of bias in normal mode and in partial mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 1 0 0 0 1 0 0 bias(2) 0 0 bias(1) bias(1): bias value selecting in normal mode and partial mode0. bias(2): bias value selecting in partial mode1. bias (2) : in partial mode 1 bias (1) : in normal mode, partial mode 0 db5 db4 bias(2) 2 ? nd boosting step db1 db0 bias(1) 2 ? nd boosting step 0 0 1/4 x( - 3) 0 0 1/4 x( - 3) 0 1 1/5 x( - 4) 0 1 1/5 x( - 4) 1 0 1/6 x( - 4) 1 0 1/6 x( - 4) 1 1 1/7 x( - 5) 1 1 1/7 x( - 5) dcdc clock division set(24h) this instruction sets the internal booster clock frequency. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 0 0 0 1 0 0 d iv(2) 0 0 div(1) div(1) : dc - dc charge pump division ratio in normal mode display and partial display mode0 - div(1) = 10 (initial status) div(2) : division ratio in partial display mode1 - div(2) = 10 (initial status) db5 db4 div(2) db1 db0 div(1) 0 0 fpck = fosc/4 0 0 fpck = fosc/4 0 1 fpck = fosc/8 0 1 fpck = fosc/8 1 0 fpck = fosc/16 1 0 fpck = fosc/16 1 1 fpck = fosc/32 1 1 fpck = fosc/32 note: fosc = ( roundup (duty/3) + dummy) x 4 x 8 x frame frequency S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 33 dc/dc and amp on/off set (26h) this instruction set up the dc/dc and op - amp in common start up setting. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 amp dcdc3 dcdc2 dcdc1 amp: built - in op - amp on/off. - amp=0: op - amp off (initial status) - amp=1: op - amp on dcdc1: built - in 1 ? st booster on/off - dcdc1= 0: 1 ? st booster off (initial status) - dcdc1= 1: 1 ? st booster on dcdc2: built - in 2 ? nd booster on/off - dcdc2= 0: 2 ? nd booster off (initial sta tus) - dcdc2= 1: 2 ? nd booster on dcdc3: built - in 3 ? rd booster on/off - dcdc3= 0: 3 ? rd booster off (initial status) - dcdc3= 1: 3 ? rd booster on temperature compensation set (28h) this instruction sets up the driving voltage slope for tempe rature compensation. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 tcs tcs: temperature compensation slope set - tcs = 00 : 0.00%/degc (initial status) - tcs = 01 : - 0.05%/degc - tcs = 10 : - 0.10%/degc - tcs = 11 : - 0.15%degc 00: 0.00 %/degc driving voltage 01: -0.05 %/degc 10: -0.10 %/degc 11: -0.15 %/degc temperature 25degc 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 34 temperature compensation if external temperature compensation is needed, circuit diagram is described as below. to use temperature compensation, two resistors and one thermistor are needed. external chip internal v1in + - v1out v1t intrs S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 35 contrast control (1) (2 ah) t his ins truction u pdates the contrast control value in normal display mode and partial display mode 0. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 0 1 contrast control value (0 to 255) the relation between v1 voltage (typ .) and contrast(1) set value ( 3bit step case) contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] contrast(1) (hex) v1 [v] 00h 2.000 30h 2.376 60h 2.753 90h 3.129 c0h 3.506 f0h 3.88 2 08h 2.063 38h 2.439 68h 2.816 98h 3.192 c8h 3.569 f8h 3.945 10h 2.125 40h 2.502 70h 2.878 a0h 3.255 d0h 3.631 ffh 4.000 18h 2.188 48h 2.565 78h 2.941 a8h 3.318 d8h 3.694 20h 2.251 50h 2.627 80h 3.004 b0h 3.380 e0h 3.757 28h 2.314 58h 2.690 88h 3.067 b8h 3.443 e8h 3.820 contrast control (2) (2bh) t his ins truction u pdates the contrast control value in partial display mode 1. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 0 1 contrast control value (0 to 255) the relation b etween v1 voltage (typ.) and contrast(2) set value ( 3 bit step case) contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] contrast(2) (hex) v1 [v] 00h 2.000 30h 2.376 60h 2.753 90h 3 .129 c0h 3.506 f0h 3.882 08h 2.063 38h 2.439 68h 2.816 98h 3.192 c8h 3.569 f8h 3.945 10h 2.125 40h 2.502 70h 2.878 a0h 3.255 d0h 3.631 ffh 4.000 18h 2.188 48h 2.565 78h 2.941 a8h 3.318 d8h 3.694 20h 2.251 50h 2.627 80h 3.004 b0h 3.380 e0h 3.757 28h 2. 314 58h 2.690 88h 3.067 b8h 3.443 e8h 3.820 note : S6B33B0A has a hardware protection for "2vr < 20v". it means the limitation of contrast value in each bias. if 1/6 bias is set, max contrast value is limited to a9h, and if 1/7 bias is set, max contrast value is limited to 6dh. 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 36 standby mode off (2ch) this instruction releases the standby mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 1 1 0 0 the internal statuses during standby off are as following: - all common and segment output: v ss or v1 - oscillator c ircuit: on (ext = 0, osc=1),off (others) - displaying clocks (fr, pm, cl): in operation function and pin condition at standby off function/pin condition dc/dc booster(1 ? st,2 ? nd,3 ? rd) on(operate) com outputs +vr or vm or vss or - v r seg outputs v1 or vss standby mode on (2dh) this instruction enters the standby mode to reduce the power consumption to the static power consumption value (initial status). the following instructions, standby off and display on, cause returning to th e normal operation status . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 1 1 0 1 the internal statuses during standby on are as following: - all common and segment o utput: vss - oscillator c ircuit: off - displaying clocks (fr, pm, cl) are held. function and pin condition at standby on function/pin condition dc/dc booster(1 ? st,2 ? nd,3 ? rd) off seg and com outputs vss lcd driving power output condition at standby on. level condition +vr vss v1 vss vm vss - vr vss S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 37 ddram burst mode off(2eh) /on(2fh) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 1 1 1 bm bm : internal ddram burst mode interface off/on control - 0 : burst mode interface off(initial status) - 1 : burst mode interface on when bm=0, if mpu[0] is 0 then internal ddram i/f bpw(bits per word) is 8 bits. else mpu[0] is 1 then internal ddram i/f bpw(bits per word) is 16bits. when bm=1, regardless of mpu[0] bit, internal ddram i/f bpw(bits per word) is 32 bits . mpu register1 00h 01h ddram x address counter 32 16 8 8 register2 02h 03h 8eh 8fh - - - - - - - - - y address counter 8 s6b33b0 figure 23 . burst mode writing to ddram 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 38 /cs e db15 ~db0 burst mode on x address setting y address setting ram data 1(16bits) - - - - - - - - - - - - - - - - - - ram data 2(16bits) ram data 3(16bits) ram data 4(16bits) - - - - - - - - - - - - - - - ram write time ram write time ram write data (32 bits) ram data 1 to 2 ram data 3 to 4 ram data 5(16bits) ram data 6(16bits) ram write time ram data 5 to 6 ram x address ram y address 00h 00h 02h 04h - - - - - - - - - - - - - - - figure 24 . example of the burst mode writing to ddram (68 - mode 16 - bit parallel interface) when ddram burst mode is used, note the following. notes: 1.data is w ritten to ddram each two words. if only one word data is written to ddram, the data will not be written. so, the number of word data must be even. it means that y start address must be even and y end address must be odd. 2.x address count mode can ? t be used. 3.burst mode and normal mode write operation cannot be executed at the same time. 4.in the read data mode and serial interface mode, the burst mode can?t be used. 5.in the 256 color mode with 16 - bit data bus mode and 4,096 color mode with 8 - bit data bus mode, the address is counted as burst mode enable. so these modes are influenced by above notes. S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 39 addressing mode set (30h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 0 0 0 0 1 0 gsm dsg sgf sgp sgm gsm: gray scale mode - 00 : 65,536 color mode(initial status) - 01 : 4,096 color mode* (refer to ? data format select(60h/61h) ? ) - 10 : 256 color mode* - 11 : 256 color mode* * in the 256 color mode with 16 - bit data bus mode and 4,096 color mode with 8 - bit data format b, the add ress is counted as burst mode enable. so, in this case, refer to notes of burst mode at page 39. dsg : duty adjust s etting - 0 : dummy subgroup is one subgroup (i nitial status ) - 1 : dummy subgroup is none sgf : sub group frame inversio n mode setting - 0: sg frame inversion off ( initial status ) - 1: sg frame inversion on sgm : sub group inversion mode setting - 0: sg inversion off ( initial status ) - 1: sg inversion on sgp : sub group phase mode setting - 00 : same phase in all pixels - 01 : different phase by 1pixel - unit - 10 : different phase by 2pixel - unit - 11 : different phase by 4pixel - unit row vector mode set (32h) setting row function. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 inc vec inc: row vector increment mode. this parameter set up row vector increment period db3 db2 db1 row vector increment period 0 0 0 every subgroup 0 0 1 every 2subgroup 0 1 0 every 4subgroup 0 1 1 every 8subgroup 1 0 0 every 16subgroup 1 0 1 every 16subgroup 1 1 0 every 16subgroup 1 1 1 every subframe vec: row vector sequence mode - 0: r1 - >r2 - >r3 - >r4 - > r1 ? .. (initial status) - 1: r1 - >r3 - >r2 - >r4 - > r1 ? .. 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 40 256 color mode palettes at 256 - color mode, the instruct ion and parameter below set each gray scale level of the red/green/blue. gray scale level is determined by gs data. red palette (38h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 0 gs data ? 000 ? to ram data 0 0 0 gs data ? 001 ? to ram data 0 0 0 gs data ? 010 ? to ram data 0 0 0 gs data ? 011 ? to ram data 0 0 0 gs data ? 100 ? to ram data 0 0 0 gs data ? 101 ? to ram data 0 0 0 gs data ? 110 ? to ram data 0 0 1 0 0 0 gs data ? 111 ? to ram data green palette (3ah) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 0 0 0 gs data ? 000 ? to ram data 0 0 gs data ? 001 ? to ram data 0 0 gs data ? 010 ? to ram data 0 0 gs data ? 011 ? to ram data 0 0 gs data ? 100 ? to ram data 0 0 gs data ? 1 01 ? to ram data 0 0 gs data ? 110 ? to ram data 0 0 1 0 0 gs data ? 111 ? to ram data blue palette (3ch) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 0 0 0 0 0 gs data ? 00 ? to ram data 0 0 0 gs data ? 01 ? to ram data 0 0 0 gs data ? 10 ? to ram data 0 0 1 0 0 0 gs data ? 11 ? to ram data S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 41 initial value for each palette initial gray scale level gray scale data red green blue 000 0 0 0 001 8 16 12 010 12 24 20 011 16 32 31 100 20 40 - 101 24 48 - 110 28 56 - 111 31 63 - the relationship between gray scale level and ram data for red/blue ram data ram data db4 db3 db2 db1 db0 gs level db4 db3 db2 db1 db0 gs level 0 0 0 0 0 0 1 0 0 0 0 16 0 0 0 0 1 1 1 0 0 0 1 17 0 0 0 1 0 2 1 0 0 1 0 18 0 0 0 1 1 3 1 0 0 1 1 19 0 0 1 0 0 4 1 0 1 0 0 20 0 0 1 0 1 5 1 0 1 0 1 21 0 0 1 1 0 6 1 0 1 1 0 22 0 0 1 1 1 7 1 0 1 1 1 23 0 1 0 0 0 8 1 1 0 0 0 24 0 1 0 0 1 9 1 1 0 0 1 25 0 1 0 1 0 10 1 1 0 1 0 26 0 1 0 1 1 11 1 1 0 1 1 27 0 1 1 0 0 12 1 1 1 0 0 28 0 1 1 0 1 13 1 1 1 0 1 29 0 1 1 1 0 14 1 1 1 1 0 30 0 1 1 1 1 15 1 1 1 1 1 31 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 42 the relationship between gray scale level and gray scale data for green gs data gs data db5 db4 db3 db2 db1 db0 gs level db5 db4 db3 db2 db1 db0 gs level 0 0 0 0 0 0 0 1 0 0 0 0 0 32 0 0 0 0 0 1 1 1 0 0 0 0 1 33 0 0 0 0 1 0 2 1 0 0 0 1 0 34 0 0 0 0 1 1 3 1 0 0 0 1 1 35 0 0 0 1 0 0 4 1 0 0 1 0 0 36 0 0 0 1 0 1 5 1 0 0 1 0 1 37 0 0 0 1 1 0 6 1 0 0 1 1 0 38 0 0 0 1 1 1 7 1 0 0 1 1 1 39 0 0 1 0 0 0 8 1 0 1 0 0 0 40 0 0 1 0 0 1 9 1 0 1 0 0 1 41 0 0 1 0 1 0 10 1 0 1 0 1 0 42 0 0 1 0 1 1 11 1 0 1 0 1 1 43 0 0 1 1 0 0 12 1 0 1 1 0 0 44 0 0 1 1 0 1 13 1 0 1 1 0 1 45 0 0 1 1 1 0 14 1 0 1 1 1 0 46 0 0 1 1 1 1 15 1 0 1 1 1 1 47 0 1 0 0 0 0 16 1 1 0 0 0 0 48 0 1 0 0 0 1 17 1 1 0 0 0 1 49 0 1 0 0 1 0 18 1 1 0 0 1 0 50 0 1 0 0 1 1 19 1 1 0 0 1 1 51 0 1 0 1 0 0 20 1 1 0 1 0 0 52 0 1 0 1 0 1 21 1 1 0 1 0 1 53 0 1 0 1 1 0 22 1 1 0 1 1 0 54 0 1 0 1 1 1 23 1 1 0 1 1 1 55 0 1 1 0 0 0 24 1 1 1 0 0 0 56 0 1 1 0 0 1 25 1 1 1 0 0 1 57 0 1 1 0 1 0 26 1 1 1 0 1 0 58 0 1 1 0 1 1 27 1 1 1 0 1 1 59 0 1 1 1 0 0 28 1 1 1 1 0 0 60 0 1 1 1 0 1 29 1 1 1 1 0 1 61 0 1 1 1 1 0 30 1 1 1 1 1 0 62 0 1 1 1 1 1 31 1 1 1 1 1 1 63 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 43 n - block inversion set (34h) this instruction set up n block inversion for ac d riving. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 1 0 0 0 0 1 fim fip 0 n - block inversion fim: forcing inversion mode fim = 0: forcing inversion off (initial status) fim = 1: forcing inversion on fip: forcing inversion period fip = 0: f orcing inversion period is one frame fip = 1: forcing inversion period is two frames n - block inversion : this parameter indicates the basic period of polarity inversion. the whole period of polarity inversion is decided by fim, fip and this pa rameter. db7 db 6 db 5 db 4 ? db0 polarity inversion period x x x 0 every frame 0 x x 1 every 1 block : : : : : 0 x x 31 every 31 blocks 1 0 x 1 every 1 block and every frame : : : : : 1 0 x 31 every 31 blocks and every frame 1 1 x 1 ever y 1 block and every 2 frames : : : : : 1 1 x 31 every 31 blocks and every 2 frames 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 44 entry mode set (40h) setting internal function mode. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 hl mdi x/y rmw hl : when gsm is 10 or 11 (256 color mode), exchange higher and lower byte in 16 - bit data bus mode only for ? display data write/read ? hl = 0: not exchanged status (initial status) hl = 1: exchanged status mdi: memory data inversion setting for low power consumption. m di = 0: memory data inversion off (initial status) mdi = 1: memory data inversion on x/y: memory address counter mode setting x/y = 0: y address counter mode (initial status) x/y = 1: x address counter mode rmw: rea d modify write mode on/off select rmw = 0: read modify write off (initial status) rmw = 1: read modify write on. when this mode is on, x(y) address of on - chip display ram is not increment in reading display data but in writing display data. x ad dress area set (42h) this instruction and parameter set up the x address areas of the on - chip display data ram . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 1 0 x start address set (initial status = 00h) 0 0 1 x end address set (initial status = afh) the current x address of the on - chip display data ram is the x start address by setting this instruction. in x address count mode (x/y = ? h ? ), the x address is increased from x start address to x end address. when x address is equal to the x end address, the y address is increased by 1 and the x address retu rns to x start address. the x start and x end addresses must be set as a pair and x start address must be less than x end address. S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 45 y address area set (43h) this instruction and parameter set up the y address areas of the on - chip display data ram . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 1 1 y start address set (initial status = 00h) 0 0 1 y end address set (initial status = 8fh) the current y address of the on - chip display data ram is the y start address by setting this instruction. in y address count mode (x/y = ? l ? ), the y address is increased from y start address to y end address. when y address is equal to the y end address, the x address is in creased by 1 and the y address retu rns to y start address. the y start and y end address must be set as a pair and y start address must be less than y end address. ram skip area set (45h) this instruction and parameter set up the x address areas of the on - chip display data ram . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 rsk rsk : ram skip function on/off set - rsk = 00 : no skip - rsk = 01 : y address 44h - 4bh skip - rsk = 10 : y address 40h - 4fh skip - rsk = 1 1 : y address 3ch - 53h skip ram skip area set ram skip area set can skip a part of ram y - address area . after setting ram skip area, y - address count skip this area and count. in other words, y address after skip area is changed into y address which a dded a part for skip area. memory data input display area skip area x - address area y - address area 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 46 display off (50h) turn the d isplay off (initial status). when display is off, all segment and co mmon output are vss level. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 0 0 function and pin condition at display off function/pin condition dc/dc booster(1 ? st,2 ? nd,3 ? rd) on(operate) seg and com outputs vss display on (51h ) turns the d isplay o n. in case of being standby mode, this instruction does not work. this instruction is executed after standby mode off. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 0 1 function and pin condition at display on fu nction/pin condition dc/dc booster(1 ? st,2 ? nd,3 ? rd) on(operate) com outputs +vr or vm or - vr seg outputs v1 or vss specified display pattern set (53h) this instruction sets the specified display pattern. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 sdp sdp : specified display pattern set - sdp = 00 : normal display - sdp = 01 : reverse display : display data reversing mode setting without the contents of the display ram - sdp = 10 : whole display pattern becomes off regardless of the ram data. - sdp = 11 : whole display pattern becomes on regardless of the ram data. S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 47 partial display mode set (55h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 pdm p t pt : partial display on/off - pt = 0 : partial display off = normal mode ( initial status) - pt = 1 : partial display on pdm: partial display mode set - pdm = 0 : partial mode 0 : duty ratio is same as normal display mode(initial status) - pdm = 1 : partial mode 1 : duty ratio is changed from normal display mode (dsg = 0 : 69 line fixed(including 1 dummy subgroup), dsg = 1 : 66 line fixed(no dummy subgroup)) applied parameter in pdm0 and pdm1 are summarized as below pdm contrast duty bias dc - dc select osc pck 0 contrast control(1) normal bias(1) dc(1) osc1 - osc2 div(1) 1 contrast control(2) 1/69 bias(2) dc(2) osc3 - osc4 div(2) operation in partial display mode 0 (pdm=0) on sc anning except partial display area - seg output select v0 or v1 level depend on ? fr ? value. refer to page51. - all of com output is fixed vm level. on scanning partial display area - it is equal to be in normal mode operation in partial display mode 1 (pdm=1) display area is from partial start line to partial end line. (com driver output is fixed vm except display area, only max69 line output com signal. on scanning except partial display area - seg output select v0 or v1 level depend on ? fr ? value. refer to page51. - all of com output is fixed vm level. on scanning partial display area - it is equal to be in normal mode display area partial start line partial end line n line pdm 0 partial start line m line 69 line fix pdm 1 no display area : no com scanning field (com = vm fixed) except partial display area : com timing is existing, but com = vm fixed partial di splay area : real display field partial end line 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 48 partial display mode0 item partial display area out of partial display area duty same as normal display mode bias same as normal display mode ( bias(1) setting ) contrast same as normal display mode ( contrast(1) setting ) oscillator same as normal display mode ( osc1 ? osc2 ) seg output level same as normal mode (v1,v0) depends on internal ? fr ? signal see page 51 com output level same as normal mode (+vr,vm, - vr) vm fixed partial display mode1 item partial display area out of partial display area out of display area duty 1/69duty bias bias(2) setting contrast contras t(2) setting oscillator ( osc3 ? osc4 ) setting value seg output level same as normal mode (v1,v0) depends on ? fr ? signal see page 51 - com output level same as normal mode (+vr, vm, - vr) vm fixed vm fixed S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 49 partial display start line set (56h), part ial display end line set(57h) these 2 instructions set the partial display area and it is possible to display a part. partial display start line set (56h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 0 1 1 0 0 0 1 partial start line partial display end line set (57h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 0 1 1 1 0 0 1 partial end line parameter set appoints display line number. at pdm 0, parameter size is able to be in a number of display lines. but that is not able to be over max 69 line at pdm 1. partial end line must set bigger number than partial start line. line 0 line 1 com 0 com 1 line 2 line 3 com 2 com 3 line 172 line 173 com 1 72 line 174 line 175 com 1 73 com 1 74 com 1 75 : : : 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 50 example of segment voltage in non - display area area scroll set (59h) this instruction sets up area scroll field (start line, end line, lower fixed line number), and it is possible to make screen to display as partial scroll field . d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 scm scroll area start line scroll area end line 0 0 1 lower fixed number scm: scroll mode setting db1 db0 mode 0 0 entire display(initial status) 0 1 upper scroll display 1 0 lower scroll display 1 1 center scroll display com partial display vm subframe +vr vm -vr v1 vm v0 addressing duty display off internal polarity counter (fr) v0 v1 v0 v1 v0 v1 v1 v0 v1 v0 vm vm vm 0 1 2 0 3 n n+1 seg frame S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 51 entire display upper display lower display center display scr oll start line set (5ah) this instruction and parameter set up scroll start line. on this instruction, scroll start line becomes the first of area scroll field . scroll operation is occurred every issue of this instruction. d/i wrb rdb db7 db6 db5 db4 db3 d b2 db1 db0 0 1 0 1 1 0 1 0 0 0 1 scroll start line 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 52 data format select (60h/61h) d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 0 0 0 0 dfs dfs : 4,096 c olor mode data format select - 0 : 4,096 color data format a (initial status) 8 bit mode : db[7:0] : xxxxrrrr (1 ? st write) db[7:0] : ggggbbbb(2 ? nd write) 16 bit mode : db[15:0] :xxxxrrrrggggbbbb (12 bit) - 1 : 4,096 color data format b 8 bit mode : db[7:0] : rrrrgggg(1 ? st write) db[7:0] : bbbbrrrr (2 ? nd write) db[7:0] : ggggbbbb(3 ? rd write) 16 bit mode : db[15:0] :rrrrggggbbbbxxxx (12 bit) normal mode normal mode partial mode 0 scroll mode scroll/partial mode 0 set partial start line set partial end line set partial mode 0 set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line set scroll mode set scroll area start line set scroll area end line set lower fixed line set scroll start line set partial start line check busy flag set partial end line set partial mode 0 release partial mode set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line set scroll mode set scroll area start line set scroll area end line set lower fixed line no. set scroll start line release partial mode S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 53 display data write/ read d/i wrb rdb db 15 ~ db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 display ram write in data 1 1 0 display ram read out data gsm = 00(65,536 color mode) (1) 16bit access mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 ? st cycle r4 r3 r2 r1 r0 g5 g4 g 3 g2 g1 g0 b4 b3 b2 b1 b0 2 ? nd cycle r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 (2) 8bit access mode 7 6 5 4 3 2 1 0 1 ? st cycle r4 r3 r2 r1 r0 g5 g4 g3 2 ? nd cycle g2 g1 g0 b4 b3 b2 b1 b0 3 ? rd cycle r4 r3 r2 r1 r0 g5 g4 g3 4 ? th cycle g2 g1 g0 b4 b 3 b2 b1 b0 gsm = 01(4,096 color mode) (1) 16bit access mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 ? st cycle x x x x r3 r2 r1 r0 g3 g2 g1 g0 b3 b2 b1 b0 2 ? nd cycle x x x x r3 r2 r1 r0 g3 g2 g1 g0 b3 b2 b1 b0 (2) 8bit access mode 7 6 5 4 3 2 1 0 1 ? st cycle x x x x r3 r2 r1 r0 2 ? nd cycle g3 g2 g1 g0 b3 b2 b1 b0 3 ? rd cycle x x x x r3 r2 r1 r0 4 ? th cycle g3 g2 g1 g0 b3 b2 b1 b0 gsm = 10 or 11 (256 color mode) (1) 16bit access mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 ? st cycle r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 2 ? nd cycle r2 r1 r0 g2 g1 g0 b1 b0 r2 r1 r0 g2 g1 g0 b1 b0 (2) 8bit access mode 7 6 5 4 3 2 1 0 1 ? st cycle r2 r1 r0 g2 g1 g0 b1 b0 2 ? nd cycle r2 r1 r0 g2 g1 g0 b1 b0 3 ? rd cycle r2 r1 r0 g2 g1 g0 b1 b0 4 ? th c ycle r2 r1 r0 g2 g1 g0 b1 b0 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 54 status read d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 bsy x/y 0 pdm pt stb rev dp this instruction indicates the internal status of the S6B33B0A. dp: ( 0 : display off status, 1 : display on status ) rev : ( 0 : di splay image non - reversing , 1 : display image r eversing ) stb : ( 0 : standby mode off status , 1 : standby mode on status ) pt: ( 0 : partial display mode off status, 1 : partial display mode on status ) p d m : ( 0 : partial display mode 0 , 1 : partial display mode 1 ) x/y: ( 0 : y - address count mode, 1 : x - address count mode ) bsy: ( 0 : no busy, 1 : busy ) set display data length (fch) this instruction is only used in 3 - pin spi mpu interface mode(ps= ? l ? , mpu[1 ] = ? l ? ). it consists of two continuous commands, the first byte control the data direction(write mode only) and inform the lcd driver the second and third bytes will be number of data bytes will be write. when di is not used, the display data length instruction is used to indicate that a specified numb er of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 1 1 1 1 1 1 0 0 number of display data upper 8bits (ddl_h) 0 0 1 number of d isplay data lower 8bits (ddl_l) S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 55 test mode1 (ffh) this instruction is for testing ic. user is not permitted to access. if access, h ave to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 1 1 1 test mode2 (feh) this instruction is fo r testing ic. user is not permitted to access. if access, h ave to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 1 1 0 test mode3 (fdh) this instruction is for testing ic. user is not permitted to access. if access, h ave to reset. d/ i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 1 0 1 test mode4 (fbh) this instruction is for testing ic. user is not permitted to access. if access, h ave to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 0 1 1 test mod e5 (fah) this instruction is for testing ic. user is not permitted to access. if access, h ave to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 0 1 0 test mode6 (f9h) this instruction is for testing ic. user is not permitted to acces s. if access, h ave to reset. d/i wrb rdb db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 1 1 0 0 1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 56 instruction parameter table 16 . instruction parameter instruction hex para . db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 ext osc oscillation mode set 0 2 h 1 * * * * * * 0 0 0 0 dln 0 sdir swp 0 driver output mode set 10 h 1 * * 0 0 * 0 0 0 0 0 0 0 dc(2) dc(1) dc - dc set 20h 1 0 0 0 0 0 0 0 0 0 0 bias(2) 0 0 bias(1) bias set 22h 1 0 * 0 0 * * 0 0 0 0 div(2) 0 0 div( 1) dcdc clock division set 24 h 1 * * 1 0 * * 1 0 0 0 0 0 amp dcdc3 dcdc2 dcdc1 dcdc and amp on/off set 26 h 1 * * * * 0 0 0 0 0 0 0 0 0 0 tcs temperature compensation set 28 h 1 * * * * * * 0 0 contrast control value in normal and partial display mode0(0 to 255) contrast control (1) 2a h 1 0 0 0 0 0 0 0 0 contrast control value in partial display mode 1(0 to 255) contrast control(2) 2b h 1 0 0 0 0 0 0 0 0 0 gsm dsg sgf sgp sgm addressing mode set 30h 1 * * 0 0 0 0 0 0 0 0 0 0 inc vec row vector mode set 32 h 1 * * * * 0 0 0 0 fim fip 0 n - block inversion n - line inversion set 34 h 1 0 0 * 0 0 0 0 0 0 0 0 0 hl mdi x/y rmw entry mode set 40 h 1 * * * * * 0 0 0 x start address set 0 0 0 0 0 0 0 0 x end address set x - address area set 4 2 h 2 1 0 1 0 1 1 1 1 y start address set 0 0 0 0 0 0 0 0 y end address set y - address area set 43h 2 1 0 0 0 1 1 1 1 0 0 0 0 0 0 rsk ram skip area set 42h 1 * * * * * * 0 0 number of display data ddl_h set display data length fch 2 number of display data ddl_l 0 0 0 0 0 0 sdp specified display pattern set 5 3 h 1 * * * * * * 0 0 0 0 0 0 0 0 pdm pt partial display mode set 55h 1 * * * * * * 0 0 partial start line partial display start line set 56h 1 0 0 0 0 0 0 0 0 partial end line partial display end line set 57h 1 0 0 0 0 0 0 0 0 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 57 table 16 . instruction parameter (continued) instruction hex para . db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 scm * * * * * * 0 0 scroll area start line 0 0 0 0 0 0 0 0 scroll area end line 1 0 1 0 1 1 1 1 lower fixed number area scroll mode set 59h 4 0 0 0 0 0 0 0 0 scroll start line scroll start line set 5ah 1 0 0 0 0 0 0 0 0 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 58 reset operation when rstb becomes ?l?, following procedure is occurred. - x start a ddress: 0, x end address: 176 - y start address: 0 , y end address: 143 - display off - read modify write mode off - function mode set mdi = 0: memory data inversion off osc = 0: oscillator off ext = 0: internal oscillator mode rev = 0: reversing mode off x/y = 0: y - address count mode standby mode on - dcdc clock division set div(1) = 10: fpck = fosc/16x div(2) = 10: fpck = fosc/16x - duty set display duty = 00h: 1/1 28 duty - dc - dc select dc(1) = 0: x1 step - up dc(2) = 0: x1 step - up - bias set bias(1) = 0h: 1/4 bias bias(2) = 0h: 1/ 4 bias - dc/dc and amp on/off set amp =0: built - in op - amp off dcdc1 =0: built - in 1 ? st booster off dcdc2 =0: built - in 2 ? nd booster off dcdc3 =0: built - in 3 ? rd booster off - n - block inversion fim =0: forcing inversion off fip =0: forcing inversion period in one frame n - block inversion = 00h: frame inversion - partial display mode pt = 0: partial display mode off pdm = 0: partial mode 0 - par tial display area set partial start line = 00h partial end line = 00h - area scroll set mode = 00h : entire d isplay scroll mode area start line: 00h area end line: af h lower fixed line number : 00h - scroll start line set scroll start l ine: 00h - addressing mode set gsm=00: 65,536 color mode dsg = 0: mode 0 sgf = 0: sg frame inversion off sgm = 0: sg reverse mode off sgp=00:same phase in all pixel - row vector mode set inc =000: increment every subgroup vec=0: r1 - >r2 - >r3 - >r4 - >r1 - > ? S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 59 power on/off seqence power on sequence power on reset waiting for releasingreset standby mode off busy flag check or waiting for osc on dcdc1 on amp on dcdc2 on no busy busy set various registers and ram data if needed (xs,xe,ys,ye,mdi,ext,rev,xy,div,dln,bias,dc, fim,fip,n-block,pt,pdm,smod,dsg,gsm,sgf, sgm,sgp,inc,vec, display data) display on dcdc3 on 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 60 power off sequence standby on ( dcdc3 off dcdc2 off amp off dcdc1 off osc off ) waiting for discharge power off display off S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 61 s pecifications absolute maximum rat ings item symbol rating unit supply v oltage range v dd3 - 0.3 to + 4.0 v l cd supply voltage range | vcc ? vee| 22 v input v oltage range v in - 0.3 to v dd +0.3 v operating t emperature range t opr - 3 0 to + 70 c storage t emperature range t str - 55 to +1 50 c operating voltage item symbol min. typ. max. unit supply v oltage (1) v dd3 1.8 - 3.3 v sup ply v oltage (2) 2vr 4.0 - 20 v supply v oltage (3) v in 2.4 3.0 3.6 v 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 62 dc characteristics (1) (v ss = 0v, v dd3 = 1.8 to 3.3 v, ta = - 3 0 to 70 c) item symbol condition min typ max uni t remarks operating voltage v dd3 1.8 3 . 3 v v dd3 operating voltage v in1 2.4 - 3.6 v v in1,vin1a operating voltage v in2 2.4 - 7.2 v operating voltage vin45 2.4 - 7.2 v vout45 1/4 bias 1.5 - 3.0 1/5 bias 1.33 - 2.67 1/6 bias 1.67 - 3.33 operating voltage dc2in 1/7 bias 1.5 - 3.0 v dc2out operating voltage 2 v r 2 v r = |(+vr) - ( - vr)| 4.0 - 20 v + v r, - vr vm 1.0 2.0 v vmout vcc 5.0 12.0 v vrp driving voltage input range vee external power supply mode - 3.0 - 8.0 v vrn high v ih 0. 8 v dd - vdd input voltage low v il vss - 0. 2 v dd v high v oh i oh = 0. 5 ma 0.8 v dd - vdd output voltage low v ol i ol = 0. 5 ma vss - 0.2vdd v input leakage current i il v in = v dd or vss - 1.0 - +1 .0 m a output leakage current i oz v in = v dd or v ss - 3.0 - +3 .0 m a normal or partial 0 f osc1 r1=80kohm (ffr=100hz target), dsg=0, 176 display lines 172.8 192.0 211.2 khz osc1 - osc2 oscillator frequency tolerance partial 1 f osc2 r1=300kohm (ffr=70hz target), 69 display lines 46.36 51.52 56.68 khz osc3 - osc4 normal or parti al 0 f osc1 (*1) 84.48 288 khz osc1 - osc2 oscillator frequency range partial 1 f osc2 (*2) 29.44 88.32 khz osc3 - osc4 driving voltage input range v1 vm 2.0 1.0 - 4.0 2.0 v regulator output range reg_out reg_enb = ? l ? 1.8 - 2.2 v (*1) minimum oscillator frequency range is defined at ffr=60hz and display line number=128 maximum oscillator frequency range is defined at ffr=150hz and display line number=176 (*2) minimum oscillator frequency range is defined at ffr=40hz and display line number=69 S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 63 maximum oscillator frequency range is defined at ffr=120hz and display line number=69 dc characteristics (2) item symbol condition min typ max unit remarks seg r on - seg v 1 = 3.0 v, v0=0v, ta = 25 c , iload=50ua - 1.5 3.0 k w segn d river output resistance com r on - com v cc = 10.5 v, vm=1.5v, vee= - 7.5v, ta = 25 c , iload=100ua - 1.0 1.5 k w comn normal mode vdd3=vin1=3.0v, v1=3.0v, bias(1)=1/6, dc(1)=x1.5, ta=25 c , display line=176 dsg=0 (1dummy) f osc 1=192.0khz (ffr=100hz) low current mode, no load, no acce ss, all white pattern - 650 750 m a c urrent consumption partial1 mode idd vdd3=vin1=3.0v, v1=3.0v, bias(2)=1/5, dc(2)=x1.5, ta=25 c , 1/69 duty f osc 2=51.52khz (ffr=70hz) low current mode, no load, no access, all white pattern - 200 250 m a vdd3 + vin1 * : ? idd ? is determined f rom lowest power consumption for dc - dc converter. 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 64 dc characteristics (3) (v ss = 0v, v dd3 = 1.8 to 3.3 v, vin1=2.4 to 3.6v, ta = - 3 0 to 70 c) item symbol condition min typ max unit remarks d (+vr) isource = 8 0ua - - 150 mv +vr d (v1) isource = 250ua - - 20 mv v1 d (vm) isource,sink = 250ua - - 20 mv vm voltage shift range(*1) d ( - vr) isink = 80ua - - 150 mv - vr (*1) voltage shift means output voltage deference between output current = iload and no - load. refer to the following figure. (in case of source current mode) item symbol condition min typ max unit remarks tole rance of bias ratio d (+vr)_0 d ( - vr)_0(*1) no load - 100 - +100 mv +vr - vr (*1) tolerance of bias ratio definition d (+vr)_0 = ((+vr) - vm ) ? vm / bias d ( - vr)_0 = ( vm - ( - vr)) ? vm / bias no-load vx vx vy vy i=0 i=iload vshift = |vx-vy| current = i load S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 65 dc characteristics (4) (v ss = 0v, v dd3 = 1.8 to 3.3 v, vi n1=2.4 to 3.6v, ta = - 3 0 to 70 c) item symbol condition min typ max unit remarks temperature compensation d vt vdd3=vin1=v1=3.0v, - 20 to 70 c - 0.02 - +0.02 %/ c v1 tolerance of contrast step of v1 d vstep 3.13 6.27 9.41 mv v1 v1 3.95 4.00 4.05 v v1 cont rast set = ffh vm 1.95 2.00 2.05 v vm v1 1.95 2.00 2.05 v v1 voltage range d v1 d vm contrast set = 00h vm 0.95 1.00 1.05 v vm condition item load current voltage range max unit ref ||+vr - vm| - |vm - ( - vr)|| i load = +100ua ( +vr) i load = - 100ua ( - vr) 100 mv fig.1 a i load = +100ua ( v1, vm ) offset voltage ||v1 - vm| - |vm - v0|| b i load = +100ua (+vr) i load = - 100ua ( - vr) +vr=5.0~12.0 v v1=2.0~4.0v vm=1.0~2.0v - vr= - 3.0~ - 8.0 v 50 mv fig.2 +vr fig. 1: offset voltage definition (+vr,vm,-vr) vx |vx-vy| < 100mv vm -vr vy +100ua -100ua v1 va |va-vb| < 50mv vm v0 vb +100ua (both case a and b) -100ua (case b) +100ua (case a) fig. 2: offset voltage definition (v1,vm,v0) 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 66 dc characteristics (5) (v ss = 0v, v dd3 = 1.8 to 3.3 v, vin1=2.4 to 3.6v, ta = - 3 0 to 70 c) range item min max v1out 2.0 v 4.0 v (dc(1) and dc(2) = x2) (*1) vmout 1.0 v 2.0 v (dc(1) and dc(2) = x2) (*2) voltage level dc2out 1.33v (1/5 bias, v1out = 2v) 3.33v (dc(1) and dc(2) = x2) (*3) (1/6 bias, v1out = 4v) if v1out input voltage is set over vin45, v1out output voltage must be clipped near vin45. in this case, v1out output level must not be unstable. refer to fig.1 v1out vin45 delta v > 0.3 v (external vin45) delta v (*1) this definition is shown as below vin45 v1out output vin45 vin45 - delta v fig. 1 v1out input delta v > 0.5 v (vin45 = vout45) if vmout input voltage is set over vin1, vmout output voltage must be clipped near vin1. in this case, vmout output level must not be unstable. refer to fig.2 vmout vin1 delta v > 0.3 v delta v (*2) this definition is shown as below vin1 vmout output vin1 vin1 - delta v fig. 2 vmout input if dc2out input voltage is set over vin2, dc2out output voltage must be clipped near vin2. in this case, vmout output level must not be unstable. refer to fig.3 dc2out vin2 delta v > 0.3 v (external vin2) delta v (*3) this definition is shown as below vin2 dc2out output vin2 vin2 - delta v fig. 3 dc2out input delta v > 0.5 v (vin2 = vout45) S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 67 ac characteristics read / write characteristics (8080 - series mpu) db 0 to db 7 (write) db 0 to db 7 (read) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pw l 80(r) , t pw l 80(w) t cy80 t ah80 t as80 / rd, / wr / cs1 ( cs2 ) d/i t pw h 80(r) , t pw h 80(w) ** t pwl80(w) and t pwl80(r) is specified in the overlapped period when cs1b is low (cs2 is high) and /wr(/rd) is low. figure 25. parallel interface (8080 - series mpu) timing diagram table 17. ac characteristics (8080 - series p arallel m ode) (v dd3 = 1.8 to 3.3 v, ta = - 30 to + 70 c) min. item signal symbol condition 3.3v 1.8v max. (3.3v/1.8v) unit address setup time address hold time d/i t as80 t ah80 0 0 0 0 - - ns system cycl e time t cy80 150 360 - ns pulse width low for write pulse width high for write wrb (wrb) t pwlw t pwhw 50 30 100 75 - - ns pulse width low for read pulse width high for read rdb (rdb) t pwlr t pwhr 50 30 100 75 - - ns data setup time data hold time t ds80 t dh80 5 8 10 14 - - ns - 60 / 120 read access time output disable time db0 to db 15 t acc80 t od80 cl = 100 pf tewhr ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 1 0 ns or less. (tr + tf) < (t cy80 - t pwl w - t pwhw ) for write, (tr + tf) < (t cy80 - t pwlr - t pwhr ) for read 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 68 read / write characteristics (6800 - series microprocessor) t dh68 t od68 t ds68 t acc68 0.9v dd 0.1v dd t e w h 68(r) , t e w h 68(w) t cy68 t ah68 t as68 db 0 to db 7 (write) e / cs1 ( cs2 ) d/i,r/w db 0 to db 7 (read) t e w l 68(r) , t e w l 68(w) ** t ewh68(w) and t ewh68(r) is specified in the overlapped period when /cs1 is low (cs2 is high) and e is high. figure 26. parallel interface (6800 - series mpu) timing diagram table 18. ac characteristics (6800 - s eries p arallel m ode) (v dd 3 = 1.8 to 3.3 v, ta = - 30 to + 70 c) min. item signal symbol condition 3.3v 1.8v max. (3.3v/1.8v) unit address setup time address hold time d/i r / w t as68 t ah6 8 0 0 0 0 - - ns system cycle time t cy68 150 360 - ns enable width high for write enable width low for write rdb (e) t ewhw t ewlw 50 30 100 75 - - ns enable width high for read enable width low for read rdb (e) t ewhr t ewlr 50 30 100 75 - - ns data setup time data hold time t ds68 t dh68 5 8 10 14 - - ns - 60 / 120 read access time output disable time db0 to db 15 t ac c68 t od68 c l = 100 pf tewlr ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 1 0 ns or less. (tr + tf) < (t cy68 - t ewhw - t ewlw ) for write, (tr + tf) < (t cy68 - t ewhr - t ewlr ) for read S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 69 serial data interface timing /cs1 sdi d /i scl t csh t sdh t sah t scyc t css t sds t sas t slw t shw t f 0. 1 v dd 0. 1 v dd t r 0.9v dd 0. 1 v dd 0.9v dd 0.1v dd (cs2) table 19. serial data interface timing (v dd 3 = 1.8 to 3.3 v, ta = - 3 0 to + 70 c) item signal symbol condition min. max. unit scl cycle time scl t csc 50 - n s scl high pulse width scl t shw 20 - n s scl low pulse width scl t slw 20 - n s sdi setup time sdi t sds 20 - n s sdi hold time sdi t sdh 20 - n s d/i setup time d/i t sas 20 - n s d/i hold time d/i t sah 20 - n s chip select setup time cs1b(cs2) t css 20 - n s chip select hold time cs1b(cs2) t chs 20 - n s 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 70 reset input timing /rst internal status t rw t r reset complete during reset figure 27. reset input timi ng diagram table 20. ac characteristics (reset mode) (v dd 3 = 1.8 to 3.3 v, ta = - 3 0 to + 70 c) item signal symbol condition min. max. unit reset low pulse width rstb t rw 1000 - ns reset t ime - t r - 1000 ns S6B33B0A preliminary ver 1 .1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd 71 system application d iagram internal power mode external components name device r1,r2 resistors c1,c2,c3 capacitors d1 schottky barrier diode value s of external capacit ors and d1 item capacitance c1 1.0 to 4.7 m f c2 1.0 to 2.2 m f c3 1.0 to 2.2 m f d1 vforward = max. 0.3v at 1ma vreverse = min. 15v maximum rating voltage of capacitors item maximum rating voltage reg_out to vss 3v vout45 to vss 11v c11p to c11m 6v c12p to c12m 6v vmout to vss 3v dc2out to vss 5v v1out to vss 6v c21p to c21m 5v c22p to c22m 10v c23p to c23m 13v c24p to c 24m 13v vss to vrn 13v c31p to c31m 17v vrp to vss 18v S6B33B0A osc1 osc2 osc3 osc4 r1 r2 osc5 /wr /rd db15db0 d/i /cs1 /wr /rd db15 to db0 mpu cs2 d/i /rst /cs1 cs2 c11 p c11m c12p c12m c2 c2 vout45 vin45 c3 vin1, vin1a vin1 vdd3, vdd3r vdd, vddo reg_out vdd3 or reg_out c1 c21p c21m c22p c22m c2 c2 c23m c24p c24m c2 c2 vrn vees, vee c3 vin2 vin2 dc2out dc2in c3 v1out v1in c3 vmout vmin c3 c31p c31m c2 vrp vcc c3 c23p v0in vss, vssa, vssb, vsso /rst d1 144 rgb seg ment & 177 common driver for 65,536 color stn lcd S6B33B0A preliminar y ver 1.1 72 external power mode S6B33B0A osc1 osc2 osc3 osc4 r1 r2 osc5 /wr /rd db15 to db0 d/i / rst /cs1 /wr /rd db15 to db0 mpu cs2 d/i /rst /cs1 cs2 c11p c11m c12p c12m vdd3, vdd3r vdd, vddo reg_out vdd3 or reg_out c vout45 vin45 vin1, vin1a vin1 c21p c21m c22p c22m c23p c23m c24p c24m vrn vees, vee vin2 vin2 dc2out dc2in v1out v1in vmout vmin c31p c31m vrp vcc v1in vmin vee vcc v0in vss, vssa, vssb, vsso |
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